OOCD_TRACE_FILES =
endif
-%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
+%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
+ %D%/riscv/libriscv.la
+
STARTUP_TCL_SRCS += %D%/startup.tcl
$(NDS32_SRC) \
$(STM8_SRC) \
$(INTEL_IA32_SRC) \
+ $(ESIRISC_SRC) \
%D%/avrt.c \
%D%/dsp563xx.c \
%D%/dsp563xx_once.c \
if TARGET64
%C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
+%C%_libtarget_la_SOURCES +=$(MIPS64_SRC)
endif
TARGET_CORE_SRC = \
%D%/target.c \
%D%/target_request.c \
%D%/testee.c \
+ %D%/semihosting_common.c \
%D%/smp.c
ARMV4_5_SRC = \
%D%/armv7m_trace.c \
%D%/cortex_m.c \
%D%/armv7a.c \
+ %D%/armv7a_mmu.c \
%D%/cortex_a.c \
- %D%/ls1_sap.c
+ %D%/ls1_sap.c \
+ %D%/mem_ap.c
ARMV8_SRC = \
%D%/armv8_dpm.c \
%D%/arm_simulator.c \
%D%/arm_semihosting.c \
%D%/arm_adi_v5.c \
+ %D%/arm_dap.c \
%D%/armv7a_cache.c \
%D%/armv7a_cache_l2x.c \
%D%/adi_v5_jtag.c \
%D%/mips32_dmaacc.c \
%D%/mips_ejtag.c
+MIPS64_SRC = \
+ %D%/mips64.c \
+ %D%/mips32_pracc.c \
+ %D%/mips64_pracc.c \
+ %D%/mips_mips64.c \
+ %D%/trace.c \
+ %D%/mips_ejtag.c
+
NDS32_SRC = \
%D%/nds32.c \
%D%/nds32_reg.c \
%D%/lakemont.c \
%D%/x86_32_common.c
+ESIRISC_SRC = \
+ %D%/esirisc.c \
+ %D%/esirisc_jtag.c \
+ %D%/esirisc_trace.c
+
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
%D%/arm.h \
%D%/arm_adi_v5.h \
%D%/armv7a_cache.h \
%D%/armv7a_cache_l2x.h \
+ %D%/armv7a_mmu.h \
%D%/arm_disassembler.h \
%D%/arm_opcodes.h \
%D%/arm_simulator.h \
%D%/etm_dummy.h \
%D%/image.h \
%D%/mips32.h \
+ %D%/mips64.h \
%D%/mips_m4k.h \
+ %D%/mips_mips64.h \
%D%/mips_ejtag.h \
%D%/mips32_pracc.h \
%D%/mips32_dmaacc.h \
+ %D%/mips64_pracc.h \
%D%/oocd_trace.h \
%D%/register.h \
%D%/target.h \
%D%/nds32_v3.h \
%D%/nds32_v3m.h \
%D%/nds32_aice.h \
+ %D%/semihosting_common.h \
%D%/stm8.h \
%D%/lakemont.h \
%D%/x86_32_common.h \
- %D%/arm_cti.h
+ %D%/arm_cti.h \
+ %D%/esirisc.h \
+ %D%/esirisc_jtag.h \
+ %D%/esirisc_regs.h \
+ %D%/esirisc_trace.h
include %D%/openrisc/Makefile.am
+include %D%/riscv/Makefile.am