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target/xtensa: avoid IHI for writes to non-executable memory
[openocd.git] / src / target / Makefile.am
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 0021f44d543802231d38eb03f56d33e222c02948..1fc7d2afa686e556d039894aa72d314c0682ce96 100644 (file)
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -1,10 +1,11 @@
-if OOCD_TRACE
-OOCD_TRACE_FILES = %D%/oocd_trace.c
-else
-OOCD_TRACE_FILES =
-endif
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
+       %D%/riscv/libriscv.la \
+       %D%/xtensa/libxtensa.la \
+       %D%/espressif/libespressif.la
 
 
-%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
+%C%_libtarget_la_CPPFLAGS = $(AM_CPPFLAGS)
 
 STARTUP_TCL_SRCS += %D%/startup.tcl
 
 
 STARTUP_TCL_SRCS += %D%/startup.tcl
 
@@ -18,16 +19,21 @@ noinst_LTLIBRARIES += %D%/libtarget.la
        $(ARM_MISC_SRC) \
        $(AVR32_SRC) \
        $(MIPS32_SRC) \
        $(ARM_MISC_SRC) \
        $(AVR32_SRC) \
        $(MIPS32_SRC) \
-       $(NDS32_SRC) \
+       $(STM8_SRC) \
        $(INTEL_IA32_SRC) \
        $(INTEL_IA32_SRC) \
+       $(ESIRISC_SRC) \
+        $(ARC_SRC) \
        %D%/avrt.c \
        %D%/dsp563xx.c \
        %D%/dsp563xx_once.c \
        %D%/dsp5680xx.c \
        %D%/avrt.c \
        %D%/dsp563xx.c \
        %D%/dsp563xx_once.c \
        %D%/dsp5680xx.c \
-       %D%/hla_target.c
+       %D%/hla_target.c \
+       $(ARMV8_SRC) \
+       $(MIPS64_SRC)
 
 
-if TARGET64
-%C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
+if HAVE_CAPSTONE
+%C%_libtarget_la_CPPFLAGS += $(CAPSTONE_CFLAGS)
+%C%_libtarget_la_LIBADD += $(CAPSTONE_LIBS)
 endif
 
 TARGET_CORE_SRC = \
 endif
 
 TARGET_CORE_SRC = \
@@ -38,7 +44,9 @@ TARGET_CORE_SRC = \
        %D%/target.c \
        %D%/target_request.c \
        %D%/testee.c \
        %D%/target.c \
        %D%/target_request.c \
        %D%/testee.c \
-       %D%/smp.c
+       %D%/semihosting_common.c \
+       %D%/smp.c \
+       %D%/rtt.c
 
 ARMV4_5_SRC = \
        %D%/armv4_5.c \
 
 ARMV4_5_SRC = \
        %D%/armv4_5.c \
@@ -70,12 +78,16 @@ ARMV7_SRC = \
        %D%/armv7m_trace.c \
        %D%/cortex_m.c \
        %D%/armv7a.c \
        %D%/armv7m_trace.c \
        %D%/cortex_m.c \
        %D%/armv7a.c \
+       %D%/armv7a_mmu.c \
        %D%/cortex_a.c \
        %D%/cortex_a.c \
-       %D%/ls1_sap.c
+       %D%/ls1_sap.c \
+       %D%/mem_ap.c
 
 ARMV8_SRC = \
        %D%/armv8_dpm.c \
 
 ARMV8_SRC = \
        %D%/armv8_dpm.c \
+       %D%/armv8_opcodes.c \
        %D%/aarch64.c \
        %D%/aarch64.c \
+       %D%/a64_disassembler.c \
        %D%/armv8.c \
        %D%/armv8_cache.c
 
        %D%/armv8.c \
        %D%/armv8_cache.c
 
@@ -86,16 +98,19 @@ ARM_DEBUG_SRC = \
        %D%/arm_simulator.c \
        %D%/arm_semihosting.c \
        %D%/arm_adi_v5.c \
        %D%/arm_simulator.c \
        %D%/arm_semihosting.c \
        %D%/arm_adi_v5.c \
+       %D%/arm_dap.c \
        %D%/armv7a_cache.c \
        %D%/armv7a_cache_l2x.c \
        %D%/armv7a_cache.c \
        %D%/armv7a_cache_l2x.c \
+       %D%/adi_v5_dapdirect.c \
        %D%/adi_v5_jtag.c \
        %D%/adi_v5_swd.c \
        %D%/embeddedice.c \
        %D%/trace.c \
        %D%/etb.c \
        %D%/etm.c \
        %D%/adi_v5_jtag.c \
        %D%/adi_v5_swd.c \
        %D%/embeddedice.c \
        %D%/trace.c \
        %D%/etb.c \
        %D%/etm.c \
-       $(OOCD_TRACE_FILES) \
-       %D%/etm_dummy.c
+       %D%/etm_dummy.c \
+       %D%/arm_tpiu_swo.c \
+       %D%/arm_cti.c
 
 AVR32_SRC = \
        %D%/avr32_ap7k.c \
 
 AVR32_SRC = \
        %D%/avr32_ap7k.c \
@@ -110,17 +125,16 @@ MIPS32_SRC = \
        %D%/mips32_dmaacc.c \
        %D%/mips_ejtag.c
 
        %D%/mips32_dmaacc.c \
        %D%/mips_ejtag.c
 
-NDS32_SRC = \
-       %D%/nds32.c \
-       %D%/nds32_reg.c \
-       %D%/nds32_cmd.c \
-       %D%/nds32_disassembler.c \
-       %D%/nds32_tlb.c \
-       %D%/nds32_v2.c \
-       %D%/nds32_v3_common.c \
-       %D%/nds32_v3.c \
-       %D%/nds32_v3m.c \
-       %D%/nds32_aice.c
+MIPS64_SRC = \
+       %D%/mips64.c \
+       %D%/mips32_pracc.c \
+       %D%/mips64_pracc.c \
+       %D%/mips_mips64.c \
+       %D%/trace.c \
+       %D%/mips_ejtag.c
+
+STM8_SRC = \
+       %D%/stm8.c
 
 INTEL_IA32_SRC = \
        %D%/quark_x10xx.c \
 
 INTEL_IA32_SRC = \
        %D%/quark_x10xx.c \
@@ -128,15 +142,29 @@ INTEL_IA32_SRC = \
        %D%/lakemont.c \
        %D%/x86_32_common.c
 
        %D%/lakemont.c \
        %D%/x86_32_common.c
 
+ESIRISC_SRC = \
+       %D%/esirisc.c \
+       %D%/esirisc_jtag.c \
+       %D%/esirisc_trace.c
+
+ARC_SRC = \
+        %D%/arc.c \
+        %D%/arc_cmd.c \
+        %D%/arc_jtag.c \
+        %D%/arc_mem.c
+
 %C%_libtarget_la_SOURCES += \
        %D%/algorithm.h \
        %D%/arm.h \
 %C%_libtarget_la_SOURCES += \
        %D%/algorithm.h \
        %D%/arm.h \
+       %D%/arm_coresight.h \
        %D%/arm_dpm.h \
        %D%/arm_jtag.h \
        %D%/arm_adi_v5.h \
        %D%/armv7a_cache.h \
        %D%/armv7a_cache_l2x.h \
        %D%/arm_dpm.h \
        %D%/arm_jtag.h \
        %D%/arm_adi_v5.h \
        %D%/armv7a_cache.h \
        %D%/armv7a_cache_l2x.h \
+       %D%/armv7a_mmu.h \
        %D%/arm_disassembler.h \
        %D%/arm_disassembler.h \
+       %D%/a64_disassembler.h \
        %D%/arm_opcodes.h \
        %D%/arm_simulator.h \
        %D%/arm_semihosting.h \
        %D%/arm_opcodes.h \
        %D%/arm_simulator.h \
        %D%/arm_semihosting.h \
@@ -172,13 +200,17 @@ INTEL_IA32_SRC = \
        %D%/etb.h \
        %D%/etm.h \
        %D%/etm_dummy.h \
        %D%/etb.h \
        %D%/etm.h \
        %D%/etm_dummy.h \
+       %D%/arm_tpiu_swo.h \
        %D%/image.h \
        %D%/mips32.h \
        %D%/image.h \
        %D%/mips32.h \
+       %D%/mips64.h \
+       %D%/mips_cpu.h \
        %D%/mips_m4k.h \
        %D%/mips_m4k.h \
+       %D%/mips_mips64.h \
        %D%/mips_ejtag.h \
        %D%/mips32_pracc.h \
        %D%/mips32_dmaacc.h \
        %D%/mips_ejtag.h \
        %D%/mips32_pracc.h \
        %D%/mips32_dmaacc.h \
-       %D%/oocd_trace.h \
+       %D%/mips64_pracc.h \
        %D%/register.h \
        %D%/target.h \
        %D%/target_type.h \
        %D%/register.h \
        %D%/target.h \
        %D%/target_type.h \
@@ -191,19 +223,22 @@ INTEL_IA32_SRC = \
        %D%/avr32_jtag.h \
        %D%/avr32_mem.h \
        %D%/avr32_regs.h \
        %D%/avr32_jtag.h \
        %D%/avr32_mem.h \
        %D%/avr32_regs.h \
-       %D%/nds32.h \
-       %D%/nds32_cmd.h \
-       %D%/nds32_disassembler.h \
-       %D%/nds32_edm.h \
-       %D%/nds32_insn.h \
-       %D%/nds32_reg.h \
-       %D%/nds32_tlb.h \
-       %D%/nds32_v2.h \
-       %D%/nds32_v3_common.h \
-       %D%/nds32_v3.h \
-       %D%/nds32_v3m.h \
-       %D%/nds32_aice.h \
+       %D%/semihosting_common.h \
+       %D%/stm8.h \
        %D%/lakemont.h \
        %D%/lakemont.h \
-       %D%/x86_32_common.h
+       %D%/x86_32_common.h \
+       %D%/arm_cti.h \
+       %D%/esirisc.h \
+       %D%/esirisc_jtag.h \
+       %D%/esirisc_regs.h \
+       %D%/esirisc_trace.h \
+       %D%/arc.h \
+       %D%/arc_cmd.h \
+       %D%/arc_jtag.h \
+       %D%/arc_mem.h \
+       %D%/rtt.h
 
 include %D%/openrisc/Makefile.am
 
 include %D%/openrisc/Makefile.am
+include %D%/riscv/Makefile.am
+include %D%/xtensa/Makefile.am
+include %D%/espressif/Makefile.am
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