if (aarch64->system_control_reg != aarch64->system_control_reg_curr) {
aarch64->system_control_reg_curr = aarch64->system_control_reg;
- retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
- 0xd5181000,
- aarch64->system_control_reg);
+ /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_v8->cp15_control_reg); */
+
+ switch (armv8->arm.core_mode) {
+ case ARMV8_64_EL0T:
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 0, 1, /* op1, op2 */
+ 0, 0, /* CRn, CRm */
+ aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 4, 1, /* op1, op2 */
+ 0, 0, /* CRn, CRm */
+ aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 6, 1, /* op1, op2 */
+ 0, 0, /* CRn, CRm */
+ aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ default:
+ LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+ }
}
-
return retval;
}
int retval = ERROR_OK;
if (enable) {
- /* if mmu enabled at target stop and mmu not enable */
+ /* if mmu enabled at target stop and mmu not enable */
if (!(aarch64->system_control_reg & 0x1U)) {
LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
return ERROR_FAIL;
}
if (!(aarch64->system_control_reg_curr & 0x1U)) {
aarch64->system_control_reg_curr |= 0x1U;
- retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
- 0xd5181000,
- aarch64->system_control_reg_curr);
+ switch (armv8->arm.core_mode) {
+ case ARMV8_64_EL0T:
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 4, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 6, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ default:
+ LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+ }
}
} else {
if (aarch64->system_control_reg_curr & 0x4U) {
}
if ((aarch64->system_control_reg_curr & 0x1U)) {
aarch64->system_control_reg_curr &= ~0x1U;
- retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
- 0xd5181000,
- aarch64->system_control_reg_curr);
+ switch (armv8->arm.core_mode) {
+ case ARMV8_64_EL0T:
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 4, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 6, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ default:
+ LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+ break;
+ }
}
}
return retval;
if (dscr & DSCR_DTR_RX_FULL) {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX */
- retval = aarch64_exec_opcode(
- a8->armv8_common.arm.target,
- 0xd5130400,
- &dscr);
+ retval = mem_ap_read_u32(a8->armv8_common.debug_ap,
+ a8->armv8_common.debug_base + CPUV8_DBG_DTRRX, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Clear sticky error */
+ retval = mem_ap_write_u32(a8->armv8_common.debug_ap,
+ a8->armv8_common.debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
if (retval != ERROR_OK)
return retval;
}
retval = aarch64_exec_opcode(
a8->armv8_common.arm.target,
- 0xd5330500,
+ ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
retval = aarch64_exec_opcode(
a8->armv8_common.arm.target,
- 0xd5330400,
+ ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
/* "Prefetch flush" after modifying execution status in CPSR */
return aarch64_exec_opcode(target,
- ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+ DSB_SY,
&dscr);
}
/* write R0 to DCC */
retval = aarch64_exec_opcode(
a8->armv8_common.arm.target,
- 0xd5130400, /* msr dbgdtr_el0, x0 */
+ ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 0), /* msr dbgdtr_el0, x0 */
&dscr);
if (retval != ERROR_OK)
return retval;
/* write R0 to DCC */
retval = aarch64_exec_opcode(
a8->armv8_common.arm.target,
- 0xd5130400, /* msr dbgdtr_el0, x0 */
+ ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), /* msr dbgdtr_el0, x0 */
&dscr);
if (retval != ERROR_OK)
return retval;
static int aarch64_debug_entry(struct target *target)
{
- uint32_t dscr;
int retval = ERROR_OK;
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = target_to_armv8(target);
- uint32_t tmp;
LOG_DEBUG("dscr = 0x%08" PRIx32, aarch64->cpudbg_dscr);
- /* REVISIT surely we should not re-read DSCR !! */
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
- if (retval != ERROR_OK)
- return retval;
-
/* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
* imprecise data aborts get discarded by issuing a Data
* Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
*/
- /* Enable the ITR execution once we are in debug mode */
- dscr |= DSCR_ITR_EN;
+ /* make sure to clear all sticky errors */
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+ armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
if (retval != ERROR_OK)
return retval;
/* Examine debug reason */
- arm_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr);
- mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_EDESR, &tmp);
- if ((tmp & 0x7) == 0x4)
- target->debug_reason = DBG_REASON_SINGLESTEP;
+ armv8_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr);
/* save address of instruction that triggered the watchpoint? */
if (target->debug_reason == DBG_REASON_WATCHPOINT) {
- uint32_t wfar;
+ uint32_t tmp;
+ uint64_t wfar = 0;
+ retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_WFAR1,
+ &tmp);
+ if (retval != ERROR_OK)
+ return retval;
+ wfar = tmp;
+ wfar = (wfar << 32);
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_WFAR0,
- &wfar);
+ &tmp);
if (retval != ERROR_OK)
return retval;
- arm_dpm_report_wfar(&armv8->dpm, wfar);
+ wfar |= tmp;
+ armv8_dpm_report_wfar(&armv8->dpm, wfar);
}
retval = armv8_dpm_read_current_registers(&armv8->dpm);
{
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = &aarch64->armv8_common;
- struct armv8_mmu_common *armv8_mmu = &armv8->armv8_mmu;
- uint32_t sctlr_el1 = 0;
int retval;
mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_DRCR, 1<<2);
- retval = aarch64_instr_read_data_r0(armv8->arm.dpm,
- 0xd5381000, &sctlr_el1);
- if (retval != ERROR_OK)
- return retval;
-
- LOG_DEBUG("sctlr_el1 = %#8.8x", sctlr_el1);
- aarch64->system_control_reg = sctlr_el1;
- aarch64->system_control_reg_curr = sctlr_el1;
- aarch64->curr_mode = armv8->arm.core_mode;
-
- armv8_mmu->mmu_enabled = sctlr_el1 & 0x1U ? 1 : 0;
- armv8_mmu->armv8_cache.d_u_cache_enabled = sctlr_el1 & 0x4U ? 1 : 0;
- armv8_mmu->armv8_cache.i_cache_enabled = sctlr_el1 & 0x1000U ? 1 : 0;
+ armv8->debug_base + CPUV8_DBG_DRCR, 1<<2);
+ switch (armv8->arm.core_mode) {
+ case ARMV8_64_EL0T:
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ retval = armv8->arm.mrs(target, 3, /*op 0*/
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ &aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ retval = armv8->arm.mrs(target, 3, /*op 0*/
+ 4, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ &aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ retval = armv8->arm.mrs(target, 3, /*op 0*/
+ 6, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ &aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ default:
+ LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+ }
+ LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
+ aarch64->system_control_reg_curr = aarch64->system_control_reg;
#if 0
if (armv8->armv8_mmu.armv8_cache.ctype == -1)
armv8_identify_cache(target);
#endif
+ armv8->armv8_mmu.mmu_enabled =
+ (aarch64->system_control_reg & 0x1U) ? 1 : 0;
+ armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
+ (aarch64->system_control_reg & 0x4U) ? 1 : 0;
+ armv8->armv8_mmu.armv8_cache.i_cache_enabled =
+ (aarch64->system_control_reg & 0x1000U) ? 1 : 0;
+ aarch64->curr_mode = armv8->arm.core_mode;
return ERROR_OK;
}
} else if (breakpoint->type == BKPT_SOFT) {
uint8_t code[4];
- buf_set_u32(code, 0, 32, 0xD4400000);
-
+ buf_set_u32(code, 0, 32, ARMV8_BKPT(0x11));
retval = target_read_memory(target,
breakpoint->address & 0xFFFFFFFFFFFFFFFE,
breakpoint->length, 1,