armv7m: add FPU registers support

[openocd.git] / src / target / arm.h

diff --git a/src/target/arm.h b/src/target/arm.h
index e2d264615570edb014a18e8bc21557d1d65b7660..27636cc3df9658c0f40dd15d57dccbbf5a8782b6 100644 (file)
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -58,8 +58,8 @@ enum arm_mode {
        ARM_MODE_FIQ = 17,
        ARM_MODE_IRQ = 18,
        ARM_MODE_SVC = 19,
+       ARM_MODE_MON = 22,
        ARM_MODE_ABT = 23,
-       ARM_MODE_MON = 26,
        ARM_MODE_UND = 27,
        ARM_MODE_SYS = 31,
 
@@ -97,7 +97,7 @@ struct arm {
        /** Handle to the PC; valid in all core modes. */
        struct reg *pc;
 
-       /** Handle to the CPSR; valid in all core modes. */
+       /** Handle to the CPSR/xPSR; valid in all core modes. */
        struct reg *cpsr;
 
        /** Handle to the SPSR; valid only in core modes with an SPSR. */
@@ -154,7 +154,7 @@ struct arm {
        int (*read_core_reg)(struct target *target, struct reg *reg,
                        int num, enum arm_mode mode);
        int (*write_core_reg)(struct target *target, struct reg *reg,
-                       int num, enum arm_mode mode, uint32_t value);
+                       int num, enum arm_mode mode, uint8_t *value);
 
        /** Read coprocessor register.  */
        int (*mrc)(struct target *target, int cpnum,
@@ -202,7 +202,7 @@ struct arm_reg {
        enum arm_mode mode;
        struct target *target;
        struct arm *arm;
-       uint32_t value;
+       uint8_t value[4];
 };
 
 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);