ARM_MODE_USER_THREAD = 1,
ARM_MODE_HANDLER = 2,
+ ARMV8_64_EL0T = 0x0,
+ ARMV8_64_EL1T = 0x4,
+ ARMV8_64_EL1H = 0x5,
+ ARMV8_64_EL2T = 0x8,
+ ARMV8_64_EL2H = 0x9,
+ ARMV8_64_EL3T = 0xC,
+ ARMV8_64_EL3H = 0xD,
+
ARM_MODE_ANY = -1
};
+/* VFPv3 internal register numbers mapping to d0:31 */
+enum {
+ ARM_VFP_V3_D0 = 51,
+ ARM_VFP_V3_D1,
+ ARM_VFP_V3_D2,
+ ARM_VFP_V3_D3,
+ ARM_VFP_V3_D4,
+ ARM_VFP_V3_D5,
+ ARM_VFP_V3_D6,
+ ARM_VFP_V3_D7,
+ ARM_VFP_V3_D8,
+ ARM_VFP_V3_D9,
+ ARM_VFP_V3_D10,
+ ARM_VFP_V3_D11,
+ ARM_VFP_V3_D12,
+ ARM_VFP_V3_D13,
+ ARM_VFP_V3_D14,
+ ARM_VFP_V3_D15,
+ ARM_VFP_V3_D16,
+ ARM_VFP_V3_D17,
+ ARM_VFP_V3_D18,
+ ARM_VFP_V3_D19,
+ ARM_VFP_V3_D20,
+ ARM_VFP_V3_D21,
+ ARM_VFP_V3_D22,
+ ARM_VFP_V3_D23,
+ ARM_VFP_V3_D24,
+ ARM_VFP_V3_D25,
+ ARM_VFP_V3_D26,
+ ARM_VFP_V3_D27,
+ ARM_VFP_V3_D28,
+ ARM_VFP_V3_D29,
+ ARM_VFP_V3_D30,
+ ARM_VFP_V3_D31,
+ ARM_VFP_V3_FPSCR,
+};
+
const char *arm_mode_name(unsigned psr_mode);
bool is_arm_mode(unsigned psr_mode);
ARM_STATE_THUMB,
ARM_STATE_JAZELLE,
ARM_STATE_THUMB_EE,
+ ARM_STATE_AARCH64,
+};
+
+/** ARM vector floating point enabled, if yes which version. */
+enum arm_vfp_version {
+ ARM_VFP_DISABLED,
+ ARM_VFP_V1,
+ ARM_VFP_V2,
+ ARM_VFP_V3,
};
#define ARM_COMMON_MAGIC 0x0A450A45
/** Flag reporting whether semihosting is active. */
bool is_semihosting;
+ /** Flag reporting whether semihosting fileio is active. */
+ bool is_semihosting_fileio;
+
+ /** Flag reporting whether semihosting fileio operation is active. */
+ bool semihosting_hit_fileio;
+
+ /** Floating point or VFP version, 0 if disabled. */
+ int arm_vfp_version;
+
+ /** Current semihosting operation. */
+ int semihosting_op;
+
+ /** Current semihosting result. */
+ int semihosting_result;
+
/** Value to be returned by semihosting SYS_ERRNO request. */
int semihosting_errno;
int (*setup_semihosting)(struct target *target, int enable);
+ /** Semihosting command line. */
+ char *semihosting_cmdline;
+
/** Backpointer to the target. */
struct target *target;
enum arm_mode mode;
struct target *target;
struct arm *arm;
- uint8_t value[4];
+ uint8_t value[16];
};
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
+struct reg_cache *armv8_build_reg_cache(struct target *target);
extern const struct command_registration arm_command_handlers[];
int arm_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size,
enum target_register_class reg_class);
+int armv8_get_gdb_reg_list(struct target *target,
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class);
int arm_init_arch_info(struct target *target, struct arm *arm);
int armv4_5_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
int timeout_ms, void *arch_info);
int armv4_5_run_algorithm_inner(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int timeout_ms, void *arch_info));
int arm_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *checksum);
+ target_addr_t address, uint32_t count, uint32_t *checksum);
int arm_blank_check_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *blank);
+ target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value);
void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
+struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
extern struct reg arm_gdb_dummy_fp_reg;
extern struct reg arm_gdb_dummy_fps_reg;