target: fix incorrect arm cpu monitor mode encoding

[openocd.git] / src / target / arm.h

diff --git a/src/target/arm.h b/src/target/arm.h
index 36763b4a0539d36c296055d0517340934ff702b0..88b5902ea8d7c9ebcd907be5b3d1dd25f00c3fd5 100644 (file)
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -21,13 +21,14 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the
  * Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  */
+
 #ifndef ARM_H
 #define ARM_H
 
-#include <target/target.h>
 #include <helper/command.h>
+#include "target.h"
 
 
 /**
@@ -40,19 +41,32 @@
  */
 
 /**
- * These numbers match the five low bits of the *PSR registers on
+ * Represent state of an ARM core.
+ *
+ * Most numbers match the five low bits of the *PSR registers on
  * "classic ARM" processors, which build on the ARMv4 processor
  * modes and register set.
+ *
+ * ARM_MODE_ANY is a magic value, often used as a wildcard.
+ *
+ * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
+ * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER.  Those are the only modes
+ * they support.
  */
 enum arm_mode {
        ARM_MODE_USR = 16,
        ARM_MODE_FIQ = 17,
        ARM_MODE_IRQ = 18,
        ARM_MODE_SVC = 19,
+       ARM_MODE_MON = 22,
        ARM_MODE_ABT = 23,
-       ARM_MODE_MON = 26,
        ARM_MODE_UND = 27,
        ARM_MODE_SYS = 31,
+
+       ARM_MODE_THREAD = 0,
+       ARM_MODE_USER_THREAD = 1,
+       ARM_MODE_HANDLER = 2,
+
        ARM_MODE_ANY = -1
 };
 
@@ -67,8 +81,6 @@ enum arm_state {
        ARM_STATE_THUMB_EE,
 };
 
-extern const char *arm_state_strings[];
-
 #define ARM_COMMON_MAGIC 0x0A450A45
 
 /**
@@ -82,7 +94,10 @@ struct arm {
        int common_magic;
        struct reg_cache *core_cache;
 
-       /** Handle to the CPSR; valid in all core modes. */
+       /** Handle to the PC; valid in all core modes. */
+       struct reg *pc;
+
+       /** Handle to the CPSR/xPSR; valid in all core modes. */
        struct reg *cpsr;
 
        /** Handle to the SPSR; valid only in core modes with an SPSR. */
@@ -96,6 +111,8 @@ struct arm {
         * ARM_MODE_ANY indicates the standard set of 37 registers,
         * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
         * more registers are shadowed, for "Secure Monitor" mode.
+        * ARM_MODE_THREAD indicates a microcontroller profile core,
+        * which only shadows SP.
         */
        enum arm_mode core_type;
 
@@ -108,12 +125,17 @@ struct arm {
        /** Flag reporting unavailability of the BKPT instruction. */
        bool is_armv4;
 
+       /** Flag reporting armv6m based core. */
+       bool is_armv6m;
+
        /** Flag reporting whether semihosting is active. */
        bool is_semihosting;
 
        /** Value to be returned by semihosting SYS_ERRNO request. */
        int semihosting_errno;
 
+       int (*setup_semihosting)(struct target *target, int enable);
+
        /** Backpointer to the target. */
        struct target *target;
 
@@ -147,17 +169,25 @@ struct arm {
                        uint32_t value);
 
        void *arch_info;
+
+       /** For targets conforming to ARM Debug Interface v5,
+        * this handle references the Debug Access Port (DAP)
+        * used to make requests to the target.
+        */
+       struct adiv5_dap *dap;
 };
 
 /** Convert target handle to generic ARM target state handle. */
 static inline struct arm *target_to_arm(struct target *target)
 {
+       assert(target != NULL);
        return target->arch_info;
 }
 
 static inline bool is_arm(struct arm *arm)
 {
-       return arm && arm->common_magic == ARM_COMMON_MAGIC;
+       assert(arm != NULL);
+       return arm->common_magic == ARM_COMMON_MAGIC;
 }
 
 struct arm_algorithm {
@@ -171,7 +201,7 @@ struct arm_reg {
        int num;
        enum arm_mode mode;
        struct target *target;
-       struct arm *armv4_5_common;
+       struct arm *arm;
        uint32_t value;
 };
 
@@ -181,7 +211,8 @@ extern const struct command_registration arm_command_handlers[];
 
 int arm_arch_state(struct target *target);
 int arm_get_gdb_reg_list(struct target *target,
-               struct reg **reg_list[], int *reg_list_size);
+               struct reg **reg_list[], int *reg_list_size,
+               enum target_register_class reg_class);
 
 int arm_init_arch_info(struct target *target, struct arm *arm);
 
@@ -207,8 +238,6 @@ int arm_blank_check_memory(struct target *target,
 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 
-void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
-
 extern struct reg arm_gdb_dummy_fp_reg;
 extern struct reg arm_gdb_dummy_fps_reg;