ARM_MODE_ANY = -1
};
+/* VFPv3 internal register numbers mapping to d0:31 */
+enum {
+ ARM_VFP_V3_D0 = 51,
+ ARM_VFP_V3_D1,
+ ARM_VFP_V3_D2,
+ ARM_VFP_V3_D3,
+ ARM_VFP_V3_D4,
+ ARM_VFP_V3_D5,
+ ARM_VFP_V3_D6,
+ ARM_VFP_V3_D7,
+ ARM_VFP_V3_D8,
+ ARM_VFP_V3_D9,
+ ARM_VFP_V3_D10,
+ ARM_VFP_V3_D11,
+ ARM_VFP_V3_D12,
+ ARM_VFP_V3_D13,
+ ARM_VFP_V3_D14,
+ ARM_VFP_V3_D15,
+ ARM_VFP_V3_D16,
+ ARM_VFP_V3_D17,
+ ARM_VFP_V3_D18,
+ ARM_VFP_V3_D19,
+ ARM_VFP_V3_D20,
+ ARM_VFP_V3_D21,
+ ARM_VFP_V3_D22,
+ ARM_VFP_V3_D23,
+ ARM_VFP_V3_D24,
+ ARM_VFP_V3_D25,
+ ARM_VFP_V3_D26,
+ ARM_VFP_V3_D27,
+ ARM_VFP_V3_D28,
+ ARM_VFP_V3_D29,
+ ARM_VFP_V3_D30,
+ ARM_VFP_V3_D31,
+ ARM_VFP_V3_FPSCR,
+};
+
const char *arm_mode_name(unsigned psr_mode);
bool is_arm_mode(unsigned psr_mode);
ARM_STATE_AARCH64,
};
+/** ARM vector floating point enabled, if yes which version. */
+enum arm_vfp_version {
+ ARM_VFP_DISABLED,
+ ARM_VFP_V1,
+ ARM_VFP_V2,
+ ARM_VFP_V3,
+};
+
#define ARM_COMMON_MAGIC 0x0A450A45
/**
/** Flag reporting whether semihosting fileio operation is active. */
bool semihosting_hit_fileio;
+ /** Floating point or VFP version, 0 if disabled. */
+ int arm_vfp_version;
+
/** Current semihosting operation. */
int semihosting_op;
enum arm_mode mode;
struct target *target;
struct arm *arm;
- uint8_t value[8];
+ uint8_t value[16];
};
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
int arm_checksum_memory(struct target *target,
target_addr_t address, uint32_t count, uint32_t *checksum);
int arm_blank_check_memory(struct target *target,
- target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value);
+ struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
struct reg *arm_reg_current(struct arm *arm, unsigned regnum);