/** Known ARM implementor IDs */
enum arm_implementor {
ARM_IMPLEMENTOR_ARM = 0x41,
+ ARM_IMPLEMENTOR_INFINEON = 0x49,
+ ARM_IMPLEMENTOR_REALTEK = 0x72,
};
/**
uint32_t crn, uint32_t crm,
uint32_t *value);
+ /** Read coprocessor to two registers. */
+ int (*mrrc)(struct target *target, int cpnum,
+ uint32_t op, uint32_t crm,
+ uint64_t *value);
+
/** Write coprocessor register. */
int (*mcr)(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t crn, uint32_t crm,
uint32_t value);
+ /** Write coprocessor from two registers. */
+ int (*mcrr)(struct target *target, int cpnum,
+ uint32_t op, uint32_t crm,
+ uint64_t value);
+
void *arch_info;
/** For targets conforming to ARM Debug Interface v5,
};
/** Convert target handle to generic ARM target state handle. */
-static inline struct arm *target_to_arm(struct target *target)
+static inline struct arm *target_to_arm(const struct target *target)
{
assert(target);
return target->arch_info;
extern const struct command_registration arm_all_profiles_command_handlers[];
int arm_arch_state(struct target *target);
-const char *arm_get_gdb_arch(struct target *target);
+const char *arm_get_gdb_arch(const struct target *target);
int arm_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size,
enum target_register_class reg_class);
-const char *armv8_get_gdb_arch(struct target *target);
+const char *armv8_get_gdb_arch(const struct target *target);
int armv8_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size,
enum target_register_class reg_class);