ARM_MODE_USER_THREAD = 1,
ARM_MODE_HANDLER = 2,
+ /* shift left 4 bits for armv8 64 */
+ ARMV8_64_EL0T = 0x0F,
+ ARMV8_64_EL1T = 0x4F,
+ ARMV8_64_EL1H = 0x5F,
+ ARMV8_64_EL2T = 0x8F,
+ ARMV8_64_EL2H = 0x9F,
+ ARMV8_64_EL3T = 0xCF,
+ ARMV8_64_EL3H = 0xDF,
+
ARM_MODE_ANY = -1
};
ARM_STATE_THUMB,
ARM_STATE_JAZELLE,
ARM_STATE_THUMB_EE,
+ ARM_STATE_AARCH64,
};
#define ARM_COMMON_MAGIC 0x0A450A45
uint32_t CRn, uint32_t CRm,
uint32_t value);
+ /** Read coprocessor register. */
+ int (*mrs)(struct target *target, uint32_t op0,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm,
+ uint32_t *value);
+
+ /** Write coprocessor register. */
+ int (*msr)(struct target *target, uint32_t cpnum,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm,
+ uint32_t value);
+
void *arch_info;
/** For targets conforming to ARM Debug Interface v5,
enum arm_mode mode;
struct target *target;
struct arm *arm;
- uint8_t value[4];
+ uint8_t value[8];
};
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
+struct reg_cache *armv8_build_reg_cache(struct target *target);
extern const struct command_registration arm_command_handlers[];
int arm_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size,
enum target_register_class reg_class);
+int armv8_get_gdb_reg_list(struct target *target,
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class);
int arm_init_arch_info(struct target *target, struct arm *arm);
void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
+struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
extern struct reg arm_gdb_dummy_fp_reg;
extern struct reg arm_gdb_dummy_fps_reg;