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added arm11 timeout error messages
[openocd.git] / src / target / arm11.c
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 6b79982c29e9cc4d87b04c8c9f8f44b791699e69..0f8faba33132b4f76a46d3411e767a6b06a0f57b 100644 (file)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2008 digenius technology GmbH.                          *
  *   Michael Bruck                                                         *
  *                                                                         *
- *   Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com              *
+ *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
  *                                                                         *
  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
  *                                                                         *
@@ -55,6 +55,7 @@ bool  arm11_config_memwrite_error_fatal               = true;
 uint32_t               arm11_vcr                                                               = 0;
 bool   arm11_config_memrw_no_increment                 = false;
 bool   arm11_config_step_irq_enable                    = false;
+bool   arm11_config_hardware_step                              = false;
 
 #define ARM11_HANDLER(x)       \
        .x                              = arm11_##x
@@ -373,6 +374,7 @@ int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
   */
 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 {
+       int retval;
        FNC_INFO;
 
        for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
@@ -458,7 +460,9 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
        for (size_t i = 0; i < 15; i++)
        {
                /* MCR p14,0,R?,c0,c5,0 */
-               arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
+               retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
+               if (retval != ERROR_OK)
+                       return retval;
        }
 
        /* save rDTR */
@@ -483,7 +487,9 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
        /* save PC */
 
        /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
-       arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
+       retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
+       if (retval != ERROR_OK)
+               return retval;
 
        /* adjust PC depending on ARM state */
 
@@ -664,6 +670,7 @@ void arm11_record_register_history(arm11_common_t * arm11)
 int arm11_poll(struct target_s *target)
 {
        FNC_INFO;
+       int retval;
 
        arm11_common_t * arm11 = target->arch_info;
 
@@ -687,7 +694,9 @@ int arm11_poll(struct target_s *target)
                        LOG_DEBUG("enter TARGET_HALTED");
                        target->state                   = TARGET_HALTED;
                        target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
-                       arm11_on_enter_debug_state(arm11);
+                       retval = arm11_on_enter_debug_state(arm11);
+                       if (retval != ERROR_OK)
+                               return retval;
 
                        target_call_event_callbacks(target,
                                old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
@@ -976,7 +985,6 @@ static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
 {
        FNC_INFO;
-       int retval;
 
        LOG_DEBUG("target->state: %s",
                target_state_name(target));
@@ -994,11 +1002,6 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
 
        LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 
-       uint32_t next_pc;
-       retval = arm11_simulate_step(target, &next_pc);
-       if (retval != ERROR_OK)
-               return retval;
-
 
        /** \todo TODO: Thumb not supported here */
 
@@ -1043,10 +1046,30 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
 
                brp[0].write    = 1;
                brp[0].address  = ARM11_SC7_BVR0;
-               brp[0].value    = R(PC);
                brp[1].write    = 1;
                brp[1].address  = ARM11_SC7_BCR0;
-               brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
+
+               if (arm11_config_hardware_step)
+               {
+                       /* hardware single stepping be used if possible or is it better to
+                        * always use the same code path? Hardware single stepping is not supported
+                        * on all hardware
+                        */
+                        brp[0].value   = R(PC);
+                        brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
+               } else
+               {
+                       /* sets a breakpoint on the next PC(calculated by simulation),
+                        */
+                       uint32_t next_pc;
+                       int retval;
+                       retval = arm11_simulate_step(target, &next_pc);
+                       if (retval != ERROR_OK)
+                               return retval;
+                               
+                       brp[0].value    = next_pc;
+                       brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
+               }
 
                CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
 
@@ -1098,11 +1121,6 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
 
        CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 
-       if (R(PC) != next_pc)
-       {
-               LOG_WARNING("next pc != simulated address %08" PRIx32 "!=%08" PRIx32, R(PC), next_pc);
-       }
-
        return ERROR_OK;
 }
 
@@ -1904,6 +1922,7 @@ BOOL_WRAPPER(memwrite_burst,                      "memory write burst mode")
 BOOL_WRAPPER(memwrite_error_fatal,             "fatal error mode for memory writes")
 BOOL_WRAPPER(memrw_no_increment,               "\"no increment\" mode for memory transfers")
 BOOL_WRAPPER(step_irq_enable,                  "IRQs while stepping")
+BOOL_WRAPPER(hardware_step,                    "hardware single step")
 
 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
@@ -2066,8 +2085,10 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
        RC_FINAL_BOOL("no_increment",                   "Don't increment address on multi-read/-write (default: disabled)",
                                                memrw_no_increment)
 
-       RC_FINAL_BOOL("step_irq_enable",                "Enable interrupts while stepping (default: disabled)",
-                                               step_irq_enable)
+RC_FINAL_BOOL("step_irq_enable",               "Enable interrupts while stepping (default: disabled)",
+                                       step_irq_enable)
+RC_FINAL_BOOL("hardware_step",         "hardware single stepping. By default use simulate + breakpoint. This command is only here to check if simulate + breakpoint implementation is broken.",
+                                       hardware_step)
 
        RC_FINAL("vcr",                                 "Control (Interrupt) Vector Catch Register",
                                                arm11_handle_vcr)
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