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ARM11: remove arm11->target
[openocd.git] / src / target / arm11.c
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 30dbedb93975cbe2cc84a693617d160a5e5ad62e..1a3e9797b3293f410839f5fc0ac70d6782e48f73 100644 (file)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -127,13 +127,14 @@ static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
                          * the target.
                          */
 
-                       arm11->target->state    = TARGET_HALTED;
-                       arm11->target->debug_reason     = arm11_get_DSCR_debug_reason(*dscr);
+                       arm11->arm.target->state = TARGET_HALTED;
+                       arm11->arm.target->debug_reason =
+                                       arm11_get_DSCR_debug_reason(*dscr);
                }
                else
                {
-                       arm11->target->state    = TARGET_RUNNING;
-                       arm11->target->debug_reason     = DBG_REASON_NOTHALTED;
+                       arm11->arm.target->state = TARGET_RUNNING;
+                       arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
                }
 
                arm11_sc7_clear_vbw(arm11);
@@ -293,12 +294,11 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11)
        return ERROR_OK;
 }
 
-/** Restore processor state
-  *
-  * This is called in preparation for the RESTART function.
-  *
-  */
-static int arm11_leave_debug_state(struct arm11_common *arm11)
+/**
+ * Restore processor state.  This is called in preparation for
+ * the RESTART function.
+ */
+static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 {
        int retval;
 
@@ -354,7 +354,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11)
        /* restore CPSR, PC, and R0 ... after flushing any modified
         * registers.
         */
-       retval = arm_dpm_write_dirty_registers(&arm11->dpm);
+       retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
 
        register_cache_invalidate(arm11->arm.core_cache);
 
@@ -598,7 +598,7 @@ static int arm11_resume(struct target *target, int current,
                arm11_sc7_set_vcr(arm11, arm11_vcr);
        }
 
-       arm11_leave_debug_state(arm11);
+       arm11_leave_debug_state(arm11, handle_breakpoints);
 
        arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 
@@ -762,7 +762,7 @@ static int arm11_step(struct target *target, int current,
                        R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
 
 
-               CHECK_RETVAL(arm11_leave_debug_state(arm11));
+               CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
 
                arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 
@@ -1203,29 +1203,6 @@ static int arm11_remove_breakpoint(struct target *target,
        return ERROR_OK;
 }
 
-static int arm11_add_watchpoint(struct target *target,
-               struct watchpoint *watchpoint)
-{
-       LOG_WARNING("Not implemented: %s", __func__);
-
-       return ERROR_FAIL;
-}
-
-static int arm11_remove_watchpoint(struct target *target,
-               struct watchpoint *watchpoint)
-{
-       LOG_WARNING("Not implemented: %s", __func__);
-
-       return ERROR_FAIL;
-}
-
-static int arm11_mrc(struct target *target, int cpnum,
-               uint32_t op1, uint32_t op2,
-               uint32_t CRn, uint32_t CRm, uint32_t *value);
-static int arm11_mcr(struct target *target, int cpnum,
-               uint32_t op1, uint32_t op2, uint32_t CRn,
-               uint32_t CRm, uint32_t value);
-
 static int arm11_target_create(struct target *target, Jim_Interp *interp)
 {
        struct arm11_common *arm11;
@@ -1245,11 +1222,6 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
 
        armv4_5_init_arch_info(target, &arm11->arm);
 
-       arm11->arm.mrc = arm11_mrc;
-       arm11->arm.mcr = arm11_mcr;
-
-       arm11->target = target;
-
        arm11->jtag_info.tap = target->tap;
        arm11->jtag_info.scann_size = 5;
        arm11->jtag_info.scann_instr = ARM11_SCAN_N;
@@ -1340,7 +1312,6 @@ static int arm11_examine(struct target *target)
 
        /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
        arm11->free_brps = arm11->brp;
-       arm11->free_wrps = arm11->wrp;
 
        LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
                        device_id, implementor, didr);
@@ -1357,10 +1328,8 @@ static int arm11_examine(struct target *target)
        /* Build register cache "late", after target_init(), since we
         * want to know if this core supports Secure Monitor mode.
         */
-       if (!target_was_examined(target)) {
-               arm11_dpm_init(arm11, didr);
-               retval = arm_dpm_setup(&arm11->dpm);
-       }
+       if (!target_was_examined(target))
+               retval = arm11_dpm_init(arm11, didr);
 
        /* ETM on ARM11 still uses original scanchain 6 access mode */
        if (arm11->arm.etm && !target_was_examined(target)) {
@@ -1379,7 +1348,8 @@ static int arm11_examine(struct target *target)
 /** Load a register that is marked !valid in the register cache */
 static int arm11_get_reg(struct reg *reg)
 {
-       struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
+       struct arm11_reg_state *r = reg->arch_info;
+       struct target *target = r->target;
 
        if (target->state != TARGET_HALTED)
        {
@@ -1400,7 +1370,8 @@ static int arm11_get_reg(struct reg *reg)
 /** Change a value in the register cache */
 static int arm11_set_reg(struct reg *reg, uint8_t *buf)
 {
-       struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
+       struct arm11_reg_state *r = reg->arch_info;
+       struct target *target = r->target;
        struct arm11_common *arm11 = target_to_arm11(target);
 //     const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
 
@@ -1520,71 +1491,6 @@ COMMAND_HANDLER(arm11_handle_vcr)
        return ERROR_OK;
 }
 
-static const uint32_t arm11_coproc_instruction_limits[] =
-{
-       15,                             /* coprocessor */
-       7,                              /* opcode 1 */
-       15,                             /* CRn */
-       15,                             /* CRm */
-       7,                              /* opcode 2 */
-       0xFFFFFFFF,             /* value */
-};
-
-static int arm11_mrc_inner(struct target *target, int cpnum,
-               uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
-               uint32_t *value, bool read)
-{
-       int retval;
-       struct arm11_common *arm11 = target_to_arm11(target);
-
-       if (target->state != TARGET_HALTED)
-       {
-               LOG_ERROR("Target not halted");
-               return ERROR_FAIL;
-       }
-
-       uint32_t instr = 0xEE000010     |
-               (cpnum <<  8) |
-               (op1 << 21) |
-               (CRn << 16) |
-               (CRm <<  0) |
-               (op2 <<  5);
-
-       if (read)
-               instr |= 0x00100000;
-
-       retval = arm11_run_instr_data_prepare(arm11);
-       if (retval != ERROR_OK)
-               return retval;
-
-       if (read)
-       {
-               retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value);
-               if (retval != ERROR_OK)
-                       return retval;
-       }
-       else
-       {
-               retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value);
-               if (retval != ERROR_OK)
-                       return retval;
-       }
-
-       return arm11_run_instr_data_finish(arm11);
-}
-
-static int arm11_mrc(struct target *target, int cpnum,
-               uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
-{
-       return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
-}
-
-static int arm11_mcr(struct target *target, int cpnum,
-               uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
-{
-       return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
-}
-
 static const struct command_registration arm11_mw_command_handlers[] = {
        {
                .name = "burst",
@@ -1680,8 +1586,6 @@ struct target_type arm11_target = {
 
        .add_breakpoint =       arm11_add_breakpoint,
        .remove_breakpoint =    arm11_remove_breakpoint,
-       .add_watchpoint =       arm11_add_watchpoint,
-       .remove_watchpoint =    arm11_remove_watchpoint,
 
        .run_algorithm =        armv4_5_run_algorithm,
 
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