#include "config.h"
#endif
-#include "arm11.h"
+#include "etm.h"
+#include "breakpoints.h"
#include "arm11_dbgtap.h"
-#include "armv4_5.h"
#include "arm_simulator.h"
#include "time_support.h"
#include "target_type.h"
+#include "algorithm.h"
+#include "register.h"
#if 0
#define ARM11_GDB_REGISTER_COUNT 26
-static uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+/* FIXME these are *identical* to the ARMv4_5 dummies ... except
+ * for their names, and being static vs global, and having different
+ * addresses. Ditto ARMv7a and ARMv7m dummies.
+ */
+
+static uint8_t arm11_gdb_dummy_fp_value[12];
static struct reg arm11_gdb_dummy_fp_reg =
{
- "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
+ .name = "GDB dummy floating-point register",
+ .value = arm11_gdb_dummy_fp_value,
+ .dirty = 0,
+ .valid = 1,
+ .size = 96,
+ .arch_info = NULL,
+ .arch_type = 0,
};
-static uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+static uint8_t arm11_gdb_dummy_fps_value[4];
static struct reg arm11_gdb_dummy_fps_reg =
{
- "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
+ .name = "GDB dummy floating-point status register",
+ .value = arm11_gdb_dummy_fps_value,
+ .dirty = 0,
+ .valid = 1,
+ .size = 32,
+ .arch_info = NULL,
+ .arch_type = 0,
};
int retval;
FNC_INFO;
- for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
+ for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
{
arm11->reg_list[i].valid = 1;
arm11->reg_list[i].dirty = 0;
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
else
{
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
arm11_record_register_history(arm11);
{
FNC_INFO;
int retval;
-
- struct arm11_common * arm11 = target->arch_info;
-
+ struct arm11_common *arm11 = target_to_arm11(target);
uint32_t dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
/* architecture specific status reply */
static int arm11_arch_state(struct target *target)
{
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
static int arm11_halt(struct target *target)
{
FNC_INFO;
-
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
LOG_DEBUG("target->state: %s",
target_state_name(target));
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
LOG_DEBUG("target->state: %s",
target_state_name(target));
brp[1].address = ARM11_SC7_BCR0 + brp_num;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
- arm11_sc7_run(arm11, brp, asizeof(brp));
+ arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
return ERROR_TARGET_NOT_HALTED;
}
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
if (!current)
R(PC) = address;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
}
- CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
/* resume */
{
FNC_INFO;
int retval;
+ struct arm11_common *arm11 = target_to_arm11(target);
- struct arm11_common * arm11 = target->arch_info;
retval = arm11_check_init(arm11, NULL);
if (retval != ERROR_OK)
return retval;
struct reg **reg_list[], int *reg_list_size)
{
FNC_INFO;
-
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
*reg_list_size = ARM11_GDB_REGISTER_COUNT;
*reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK)
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK)
return arm11_write_memory(target, address, 4, count, buffer);
}
-/* here we have nothing target specific to contribute, so we fail and then the
- * fallback code will read data from the target and calculate the CRC on the
- * host.
- */
-static int arm11_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t* checksum)
-{
- return ERROR_FAIL;
-}
-
/* target break-/watchpoint control
* rw: 0 = write, 1 = read, 2 = access
*/
struct breakpoint *breakpoint)
{
FNC_INFO;
-
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
#if 0
if (breakpoint->type == BKPT_SOFT)
struct breakpoint *breakpoint)
{
FNC_INFO;
-
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
arm11->free_brps++;
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info)
{
- struct arm11_common *arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
// enum armv4_5_state core_state = arm11->core_state;
// enum armv4_5_mode core_mode = arm11->core_mode;
uint32_t context[16];
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- exit(-1);
+ return ERROR_INVALID_ARGUMENTS;
}
if (reg->size != reg_params[i].size)
{
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- exit(-1);
+ return ERROR_INVALID_ARGUMENTS;
}
arm11_set_reg(reg,reg_params[i].value);
// printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- exit(-1);
+ retval = ERROR_INVALID_ARGUMENTS;
+ goto del_breakpoint;
}
if (reg->size != reg_params[i].size)
{
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- exit(-1);
+ retval = ERROR_INVALID_ARGUMENTS;
+ goto del_breakpoint;
}
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
return ERROR_COMMAND_SYNTAX_ERROR;
}
- target->arch_info = arm11;
+ armv4_5_init_arch_info(target, &arm11->arm);
+
+ arm11->jtag_info.tap = target->tap;
+ arm11->jtag_info.scann_size = 5;
+ arm11->jtag_info.scann_instr = ARM11_SCAN_N;
+ /* cur_scan_chain == 0 */
+ arm11->jtag_info.intest_instr = ARM11_INTEST;
return ERROR_OK;
}
int retval;
FNC_INFO;
-
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
/* check IDCODE */
arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
- arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
case 0x07B56000: LOG_INFO("found ARM1156"); break;
case 0x07B76000: LOG_INFO("found ARM1176"); break;
default:
- {
LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
return ERROR_FAIL;
}
- }
arm11->debug_version = (arm11->didr >> 16) & 0x0F;
if (retval != ERROR_OK)
return retval;
+ /* ETM on ARM11 still uses original scanchain 6 access mode */
+ if (arm11->arm.etm && !target_was_examined(target)) {
+ *register_get_last_cache_p(&target->reg_cache) =
+ etm_build_reg_cache(target, &arm11->jtag_info,
+ arm11->arm.etm);
+ retval = etm_setup(target);
+ }
+
target_set_examined(target);
return ERROR_OK;
/** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
#if 0
- struct arm11_common *arm11 = target->arch_info;
- const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
+ struct arm11_common *arm11 = target_to_arm11(target);
+ const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
#endif
return ERROR_OK;
{
FNC_INFO;
- struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
- struct arm11_common *arm11 = target->arch_info;
-// const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
+ struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
+ struct arm11_common *arm11 = target_to_arm11(target);
+// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
reg->valid = 1;
static int arm11_build_reg_cache(struct target *target)
{
- struct arm11_common *arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
NEW(struct reg_cache, cache, 1);
NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT);
size_t i;
/* Not very elegant assertion */
- if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
- ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
+ if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
+ ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
{
- LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
+ LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, ARRAY_SIZE(arm11->reg_values), ARRAY_SIZE(arm11_reg_defs), ARM11_RC_MAX);
exit(-1);
}
r->value = (uint8_t *)(arm11->reg_values + i);
r->dirty = 0;
r->valid = 0;
- r->bitfield_desc = NULL;
- r->num_bitfields = 0;
r->arch_type = arm11_regs_arch_type;
r->arch_info = rs;
0xFFFFFFFF, /* value */
};
-static struct arm11_common * arm11_find_target(const char * arg)
-{
- struct jtag_tap * tap;
- struct target * t;
-
- tap = jtag_tap_by_string(arg);
-
- if (!tap)
- return 0;
-
- for (t = all_targets; t; t = t->next)
- {
- if (t->tap != tap)
- continue;
-
- /* if (t->type == arm11_target) */
- if (0 == strcmp(target_get_name(t), "arm11"))
- return t->arch_info;
- }
-
- return 0;
-}
-
static int arm11_mrc_inner(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
uint32_t *value, bool read)
{
int retval;
-
+ struct arm11_common *arm11 = target_to_arm11(target);
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_FAIL;
}
-
- struct arm11_common * arm11 = target->arch_info;
uint32_t instr = 0xEE000010 |
(cpnum << 8) |
return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
}
-static COMMAND_HELPER(arm11_handle_etm_read_write, bool read)
-{
- if (argc != (read ? 2 : 3))
- {
- LOG_ERROR("Invalid number of arguments.");
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- struct arm11_common * arm11 = arm11_find_target(args[0]);
-
- if (!arm11)
- {
- LOG_ERROR("Parameter 1 is not the target name of an ARM11 device.");
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- uint32_t address;
- COMMAND_PARSE_NUMBER(u32, args[1], address);
-
- if (!read)
- {
- uint32_t value;
- COMMAND_PARSE_NUMBER(u32, args[2], value);
-
- LOG_INFO("ETM write register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
- address, address, value, value);
-
- CHECK_RETVAL(arm11_write_etm(arm11, address, value));
- }
- else
- {
- uint32_t value;
-
- CHECK_RETVAL(arm11_read_etm(arm11, address, &value));
-
- LOG_INFO("ETM read register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
- address, address, value, value);
- }
-
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(arm11_handle_etmr)
-{
- return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, true);
-}
-
-COMMAND_HANDLER(arm11_handle_etmw)
-{
- return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, false);
-}
-
-#define ARM11_HANDLER(x) .x = arm11_##x
-
-struct target_type arm11_target = {
- .name = "arm11",
-
- ARM11_HANDLER(poll),
- ARM11_HANDLER(arch_state),
-
- ARM11_HANDLER(target_request_data),
-
- ARM11_HANDLER(halt),
- ARM11_HANDLER(resume),
- ARM11_HANDLER(step),
-
- ARM11_HANDLER(assert_reset),
- ARM11_HANDLER(deassert_reset),
- ARM11_HANDLER(soft_reset_halt),
-
- ARM11_HANDLER(get_gdb_reg_list),
-
- ARM11_HANDLER(read_memory),
- ARM11_HANDLER(write_memory),
-
- ARM11_HANDLER(bulk_write_memory),
-
- ARM11_HANDLER(checksum_memory),
-
- ARM11_HANDLER(add_breakpoint),
- ARM11_HANDLER(remove_breakpoint),
- ARM11_HANDLER(add_watchpoint),
- ARM11_HANDLER(remove_watchpoint),
-
- ARM11_HANDLER(run_algorithm),
-
- ARM11_HANDLER(register_commands),
- ARM11_HANDLER(target_create),
- ARM11_HANDLER(init_target),
- ARM11_HANDLER(examine),
-
- ARM11_HANDLER(mrc),
- ARM11_HANDLER(mcr),
- };
-
-
-int arm11_register_commands(struct command_context *cmd_ctx)
+static int arm11_register_commands(struct command_context *cmd_ctx)
{
FNC_INFO;
struct command *top_cmd, *mw_cmd;
+ armv4_5_register_commands(cmd_ctx);
+
top_cmd = register_command(cmd_ctx, NULL, "arm11",
NULL, COMMAND_ANY, NULL);
- register_command(cmd_ctx, top_cmd, "etmr",
- arm11_handle_etmr, COMMAND_ANY,
- "Read Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address>");
-
- register_command(cmd_ctx, top_cmd, "etmw",
- arm11_handle_etmw, COMMAND_ANY,
- "Write Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address> <value>");
-
/* "hardware_step" is only here to check if the default
* simulate + breakpoint implementation is broken.
* TEMPORARY! NOT DOCUMENTED!
arm11_handle_vcr, COMMAND_ANY,
"Control (Interrupt) Vector Catch Register");
- return ERROR_OK;
+ return etm_register_commands(cmd_ctx);
}
+
+/** Holds methods for ARM11xx targets. */
+struct target_type arm11_target = {
+ .name = "arm11",
+
+ .poll = arm11_poll,
+ .arch_state = arm11_arch_state,
+
+ .target_request_data = arm11_target_request_data,
+
+ .halt = arm11_halt,
+ .resume = arm11_resume,
+ .step = arm11_step,
+
+ .assert_reset = arm11_assert_reset,
+ .deassert_reset = arm11_deassert_reset,
+ .soft_reset_halt = arm11_soft_reset_halt,
+
+ .get_gdb_reg_list = arm11_get_gdb_reg_list,
+
+ .read_memory = arm11_read_memory,
+ .write_memory = arm11_write_memory,
+
+ .bulk_write_memory = arm11_bulk_write_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
+
+ .add_breakpoint = arm11_add_breakpoint,
+ .remove_breakpoint = arm11_remove_breakpoint,
+ .add_watchpoint = arm11_add_watchpoint,
+ .remove_watchpoint = arm11_remove_watchpoint,
+
+ .run_algorithm = arm11_run_algorithm,
+
+ .register_commands = arm11_register_commands,
+ .target_create = arm11_target_create,
+ .init_target = arm11_init_target,
+ .examine = arm11_examine,
+
+ .mrc = arm11_mrc,
+ .mcr = arm11_mcr,
+};
Code Review / openocd.git / blobdiff