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semihosting: fix accessing memory outside the bounds of the fn array
[openocd.git] / src / target / arm11.c
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 68d4e18944324e076053ce0b2e35005873c5ef77..e3b0975fb38b228e56fa8d9f687c2d02ec6f1071 100644 (file)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -51,14 +51,14 @@ static int arm11_step(struct target *target, int current,
  */
 static int arm11_check_init(struct arm11_common *arm11)
 {
-       CHECK_RETVAL(arm11_read_DSCR(arm11));
+       CHECK_RETVAL(arm11_read_dscr(arm11));
 
        if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) {
                LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
                LOG_DEBUG("Bringing target into debug mode");
 
                arm11->dscr |= DSCR_HALT_DBG_MODE;
-               CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
+               CHECK_RETVAL(arm11_write_dscr(arm11, arm11->dscr));
 
                /* add further reset initialization here */
 
@@ -104,9 +104,9 @@ static int arm11_debug_entry(struct arm11_common *arm11)
        /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
        arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
        if (arm11->is_wdtr_saved) {
-               arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
+               arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT);
 
-               arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+               arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
                struct scan_field chain5_fields[3];
 
@@ -126,7 +126,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
         * but not to issue ITRs(?).  The ARMv7 arch spec says it's required
         * for executing instructions via ITR.
         */
-       CHECK_RETVAL(arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr));
+       CHECK_RETVAL(arm11_write_dscr(arm11, DSCR_ITR_EN | arm11->dscr));
 
 
        /* From the spec:
@@ -143,14 +143,14 @@ static int arm11_debug_entry(struct arm11_common *arm11)
                /* mcr     15, 0, r0, cr7, cr10, {4} */
                arm11_run_instr_no_data1(arm11, 0xee070f9a);
 
-               uint32_t dscr = arm11_read_DSCR(arm11);
+               uint32_t dscr = arm11_read_dscr(arm11);
 
                LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 
                if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) {
                        arm11_run_instr_no_data1(arm11, 0xe320f000);
 
-                       dscr = arm11_read_DSCR(arm11);
+                       dscr = arm11_read_dscr(arm11);
 
                        LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 
@@ -242,7 +242,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
        /* spec says clear wDTR and rDTR; we assume they are clear as
           otherwise our programming would be sloppy */
        {
-               CHECK_RETVAL(arm11_read_DSCR(arm11));
+               CHECK_RETVAL(arm11_read_dscr(arm11));
 
                if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) {
                        /*
@@ -285,23 +285,23 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
        register_cache_invalidate(arm11->arm.core_cache);
 
        /* restore DSCR */
-       CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
+       CHECK_RETVAL(arm11_write_dscr(arm11, arm11->dscr));
 
        /* maybe restore rDTR */
        if (arm11->is_rdtr_saved) {
-               arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
+               arm11_add_debug_scan_n(arm11, 0x05, ARM11_TAP_DEFAULT);
 
-               arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
+               arm11_add_ir(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 
                struct scan_field chain5_fields[3];
 
-               uint8_t Ready           = 0;                    /* ignored */
-               uint8_t Valid           = 0;                    /* ignored */
+               uint8_t ready           = 0;                    /* ignored */
+               uint8_t valid           = 0;                    /* ignored */
 
                arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
                        NULL, chain5_fields + 0);
-               arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
-               arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
+               arm11_setup_field(arm11,  1, &ready,    NULL, chain5_fields + 1);
+               arm11_setup_field(arm11,  1, &valid,    NULL, chain5_fields + 2);
 
                arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
                                chain5_fields), chain5_fields, TAP_DRPAUSE);
@@ -355,8 +355,7 @@ static int arm11_arch_state(struct target *target)
        /* REVISIT also display ARM11-specific MMU and cache status ... */
 
        if (target->debug_reason == DBG_REASON_WATCHPOINT)
-               LOG_USER("Watchpoint triggered at PC %#08x",
-                       (unsigned) arm11->dpm.wp_pc);
+               LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, arm11->dpm.wp_addr);
 
        return retval;
 }
@@ -377,14 +376,14 @@ static int arm11_halt(struct target *target)
                return ERROR_OK;
        }
 
-       arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
+       arm11_add_ir(arm11, ARM11_HALT, TAP_IDLE);
 
        CHECK_RETVAL(jtag_execute_queue());
 
        int i = 0;
 
        while (1) {
-               CHECK_RETVAL(arm11_read_DSCR(arm11));
+               CHECK_RETVAL(arm11_read_dscr(arm11));
 
                if (arm11->dscr & DSCR_CORE_HALTED)
                        break;
@@ -520,13 +519,13 @@ static int arm11_resume(struct target *target, int current,
        /* activate all watchpoints and breakpoints */
        CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
 
-       arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
+       arm11_add_ir(arm11, ARM11_RESTART, TAP_IDLE);
 
        CHECK_RETVAL(jtag_execute_queue());
 
        int i = 0;
        while (1) {
-               CHECK_RETVAL(arm11_read_DSCR(arm11));
+               CHECK_RETVAL(arm11_read_dscr(arm11));
 
                LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
 
@@ -662,7 +661,7 @@ static int arm11_step(struct target *target, int current,
 
                CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
 
-               arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
+               arm11_add_ir(arm11, ARM11_RESTART, TAP_IDLE);
 
                CHECK_RETVAL(jtag_execute_queue());
 
@@ -673,7 +672,7 @@ static int arm11_step(struct target *target, int current,
                        const uint32_t mask = DSCR_CORE_RESTARTED
                                | DSCR_CORE_HALTED;
 
-                       CHECK_RETVAL(arm11_read_DSCR(arm11));
+                       CHECK_RETVAL(arm11_read_dscr(arm11));
                        LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
 
                        if ((arm11->dscr & mask) == mask)
@@ -1097,7 +1096,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
 {
        struct arm11_common *arm11;
 
-       if (target->tap == NULL)
+       if (!target->tap)
                return ERROR_FAIL;
 
        if (target->tap->ir_length != 5) {
@@ -1152,7 +1151,7 @@ static int arm11_examine(struct target *target)
 
        /* check IDCODE */
 
-       arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
+       arm11_add_ir(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
 
        struct scan_field idcode_field;
 
@@ -1162,9 +1161,9 @@ static int arm11_examine(struct target *target)
 
        /* check DIDR */
 
-       arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
+       arm11_add_debug_scan_n(arm11, 0x00, ARM11_TAP_DEFAULT);
 
-       arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+       arm11_add_ir(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
        struct scan_field chain0_fields[2];
 
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