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arm11_sc7_action_t -> struct arm11_sc7_action
[openocd.git] / src / target / arm11.c
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 1dc1834bb4656c3782a5b5f9a16fb92de4f6035f..e5794b8ae53ddcdf593587615fcbee25b0e88c22 100644 (file)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -87,16 +87,16 @@ enum arm11_regtype
 };
 
 
-typedef struct arm11_reg_defs_s
+struct arm11_reg_defs
 {
        char *                                  name;
        uint32_t                                                num;
        int                                             gdb_num;
        enum arm11_regtype              type;
-} arm11_reg_defs_t;
+};
 
 /* update arm11_regcache_ids when changing this */
-static const arm11_reg_defs_t arm11_reg_defs[] =
+static const struct arm11_reg_defs arm11_reg_defs[] =
 {
        {"r0",  0,      0,      ARM11_REGISTER_CORE},
        {"r1",  1,      1,      ARM11_REGISTER_CORE},
@@ -261,7 +261,7 @@ static reg_t arm11_gdb_dummy_fps_reg =
 };
 
 
-static int arm11_on_enter_debug_state(arm11_common_t *arm11);
+static int arm11_on_enter_debug_state(struct arm11_common *arm11);
 static int arm11_step(struct target_s *target, int current,
                uint32_t address, int handle_breakpoints);
 /* helpers */
@@ -269,8 +269,8 @@ static int arm11_build_reg_cache(target_t *target);
 static int arm11_set_reg(reg_t *reg, uint8_t *buf);
 static int arm11_get_reg(reg_t *reg);
 
-static void arm11_record_register_history(arm11_common_t * arm11);
-static void arm11_dump_reg_changes(arm11_common_t * arm11);
+static void arm11_record_register_history(struct arm11_common * arm11);
+static void arm11_dump_reg_changes(struct arm11_common * arm11);
 
 
 /** Check and if necessary take control of the system
@@ -280,7 +280,7 @@ static void arm11_dump_reg_changes(arm11_common_t * arm11);
  *                                     available a pointer to a word holding the
  *                                     DSCR can be passed. Otherwise use NULL.
  */
-static int arm11_check_init(arm11_common_t *arm11, uint32_t *dscr)
+static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
 {
        FNC_INFO;
 
@@ -338,7 +338,7 @@ static int arm11_check_init(arm11_common_t *arm11, uint32_t *dscr)
   * or on other occasions that stop the processor.
   *
   */
-static int arm11_on_enter_debug_state(arm11_common_t *arm11)
+static int arm11_on_enter_debug_state(struct arm11_common *arm11)
 {
        int retval;
        FNC_INFO;
@@ -360,7 +360,7 @@ static int arm11_on_enter_debug_state(arm11_common_t *arm11)
 
                arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-               scan_field_t    chain5_fields[3];
+               struct scan_field       chain5_fields[3];
 
                arm11_setup_field(arm11, 32, NULL, &R(WDTR),    chain5_fields + 0);
                arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
@@ -502,7 +502,7 @@ static int arm11_on_enter_debug_state(arm11_common_t *arm11)
        return ERROR_OK;
 }
 
-void arm11_dump_reg_changes(arm11_common_t * arm11)
+void arm11_dump_reg_changes(struct arm11_common * arm11)
 {
 
        if (!(debug_level >= LOG_LVL_DEBUG))
@@ -537,7 +537,7 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
   * This is called in preparation for the RESTART function.
   *
   */
-static int arm11_leave_debug_state(arm11_common_t *arm11)
+static int arm11_leave_debug_state(struct arm11_common *arm11)
 {
        FNC_INFO;
        int retval;
@@ -637,7 +637,7 @@ static int arm11_leave_debug_state(arm11_common_t *arm11)
 
                arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 
-               scan_field_t    chain5_fields[3];
+               struct scan_field       chain5_fields[3];
 
                uint8_t                 Ready           = 0;    /* ignored */
                uint8_t                 Valid           = 0;    /* ignored */
@@ -654,7 +654,7 @@ static int arm11_leave_debug_state(arm11_common_t *arm11)
        return ERROR_OK;
 }
 
-static void arm11_record_register_history(arm11_common_t *arm11)
+static void arm11_record_register_history(struct arm11_common *arm11)
 {
        for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
        {
@@ -673,7 +673,7 @@ static int arm11_poll(struct target_s *target)
        FNC_INFO;
        int retval;
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        uint32_t        dscr;
 
@@ -715,7 +715,7 @@ static int arm11_poll(struct target_s *target)
 /* architecture specific status reply */
 static int arm11_arch_state(struct target_s *target)
 {
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
                         Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
@@ -739,7 +739,7 @@ static int arm11_halt(struct target_s *target)
 {
        FNC_INFO;
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        LOG_DEBUG("target->state: %s",
                target_state_name(target));
@@ -808,7 +808,7 @@ static int arm11_resume(struct target_s *target, int current,
        //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
        //      current, address, handle_breakpoints, debug_execution);
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        LOG_DEBUG("target->state: %s",
                target_state_name(target));
@@ -851,7 +851,7 @@ static int arm11_resume(struct target_s *target, int current,
 
                for (bp = target->breakpoints; bp; bp = bp->next)
                {
-                       arm11_sc7_action_t      brp[2];
+                       struct arm11_sc7_action brp[2];
 
                        brp[0].write    = 1;
                        brp[0].address  = ARM11_SC7_BVR0 + brp_num;
@@ -944,7 +944,7 @@ static int armv4_5_to_arm11(int reg)
 
 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
 {
-       arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+       struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
        reg=armv4_5_to_arm11(reg);
 
@@ -954,7 +954,7 @@ static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
 static void arm11_sim_set_reg(struct arm_sim_interface *sim,
                int reg, uint32_t value)
 {
-       arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+       struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
        reg=armv4_5_to_arm11(reg);
 
@@ -964,14 +964,14 @@ static void arm11_sim_set_reg(struct arm_sim_interface *sim,
 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
                int pos, int bits)
 {
-       arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+       struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
        return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
 }
 
 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
 {
-//     arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+//     struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
        /* FIX!!!! we should implement thumb for arm11 */
        return ARMV4_5_STATE_ARM;
@@ -980,7 +980,7 @@ static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
 static void arm11_sim_set_state(struct arm_sim_interface *sim,
                enum armv4_5_state mode)
 {
-//     arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+//     struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
        /* FIX!!!! we should implement thumb for arm11 */
        LOG_ERROR("Not implemetned!");
@@ -989,7 +989,7 @@ static void arm11_sim_set_state(struct arm_sim_interface *sim,
 
 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
 {
-       //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+       //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
        /* FIX!!!! we should implement something that returns the current mode here!!! */
        return ARMV4_5_MODE_USR;
@@ -1027,7 +1027,7 @@ static int arm11_step(struct target_s *target, int current,
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        if (!current)
                R(PC) = address;
@@ -1074,7 +1074,7 @@ static int arm11_step(struct target_s *target, int current,
 
                /* Set up breakpoint for stepping */
 
-               arm11_sc7_action_t      brp[2];
+               struct arm11_sc7_action brp[2];
 
                brp[0].write    = 1;
                brp[0].address  = ARM11_SC7_BVR0;
@@ -1174,7 +1174,7 @@ static int arm11_assert_reset(target_t *target)
        FNC_INFO;
        int retval;
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
        retval = arm11_check_init(arm11, NULL);
        if (retval != ERROR_OK)
                return retval;
@@ -1249,7 +1249,7 @@ static int arm11_get_gdb_reg_list(struct target_s *target,
 {
        FNC_INFO;
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        *reg_list_size  = ARM11_GDB_REGISTER_COUNT;
        *reg_list               = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
@@ -1297,7 +1297,7 @@ static int arm11_read_memory_inner(struct target_s *target,
 
        LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        retval = arm11_run_instr_data_prepare(arm11);
        if (retval != ERROR_OK)
@@ -1393,7 +1393,7 @@ static int arm11_write_memory_inner(struct target_s *target,
 
        LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        retval = arm11_run_instr_data_prepare(arm11);
        if (retval != ERROR_OK)
@@ -1556,7 +1556,7 @@ static int arm11_add_breakpoint(struct target_s *target,
 {
        FNC_INFO;
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
 #if 0
        if (breakpoint->type == BKPT_SOFT)
@@ -1588,7 +1588,7 @@ static int arm11_remove_breakpoint(struct target_s *target,
 {
        FNC_INFO;
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        arm11->free_brps++;
 
@@ -1614,12 +1614,12 @@ static int arm11_remove_watchpoint(struct target_s *target,
 // HACKHACKHACK - FIXME mode/state
 /* target algorithm support */
 static int arm11_run_algorithm(struct target_s *target,
-               int num_mem_params, mem_param_t *mem_params,
-               int num_reg_params, reg_param_t *reg_params,
+               int num_mem_params, struct mem_param *mem_params,
+               int num_reg_params, struct reg_param *reg_params,
                uint32_t entry_point, uint32_t exit_point,
                int timeout_ms, void *arch_info)
 {
-               arm11_common_t *arm11 = target->arch_info;
+               struct arm11_common *arm11 = target->arch_info;
 //     enum armv4_5_state core_state = arm11->core_state;
 //     enum armv4_5_mode core_mode = arm11->core_mode;
        uint32_t context[16];
@@ -1783,7 +1783,7 @@ static int arm11_target_create(struct target_s *target, Jim_Interp *interp)
 {
        FNC_INFO;
 
-       NEW(arm11_common_t, arm11, 1);
+       NEW(struct arm11_common, arm11, 1);
 
        arm11->target = target;
 
@@ -1815,13 +1815,13 @@ static int arm11_examine(struct target_s *target)
 
        FNC_INFO;
 
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        /* check IDCODE */
 
        arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
 
-       scan_field_t            idcode_field;
+       struct scan_field               idcode_field;
 
        arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
 
@@ -1833,7 +1833,7 @@ static int arm11_examine(struct target_s *target)
 
        arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-       scan_field_t            chain0_fields[2];
+       struct scan_field               chain0_fields[2];
 
        arm11_setup_field(arm11, 32, NULL,      &arm11->didr,           chain0_fields + 0);
        arm11_setup_field(arm11,  8, NULL,      &arm11->implementor,    chain0_fields + 1);
@@ -1895,7 +1895,7 @@ static int arm11_get_reg(reg_t *reg)
 {
        FNC_INFO;
 
-       target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
+       target_t * target = ((struct arm11_reg_state *)reg->arch_info)->target;
 
        if (target->state != TARGET_HALTED)
        {
@@ -1906,8 +1906,8 @@ static int arm11_get_reg(reg_t *reg)
        /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
 
 #if 0
-       arm11_common_t *arm11 = target->arch_info;
-       const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
+       struct arm11_common *arm11 = target->arch_info;
+       const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
 #endif
 
        return ERROR_OK;
@@ -1918,11 +1918,11 @@ static int arm11_set_reg(reg_t *reg, uint8_t *buf)
 {
        FNC_INFO;
 
-       target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
-       arm11_common_t *arm11 = target->arch_info;
-//       const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
+       target_t * target = ((struct arm11_reg_state *)reg->arch_info)->target;
+       struct arm11_common *arm11 = target->arch_info;
+//       const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
 
-       arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
+       arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
        reg->valid      = 1;
        reg->dirty      = 1;
 
@@ -1931,11 +1931,11 @@ static int arm11_set_reg(reg_t *reg, uint8_t *buf)
 
 static int arm11_build_reg_cache(target_t *target)
 {
-       arm11_common_t *arm11 = target->arch_info;
+       struct arm11_common *arm11 = target->arch_info;
 
        NEW(reg_cache_t,                cache,                          1);
        NEW(reg_t,                              reg_list,                       ARM11_REGCACHE_COUNT);
-       NEW(arm11_reg_state_t,  arm11_reg_states,       ARM11_REGCACHE_COUNT);
+       NEW(struct arm11_reg_state,     arm11_reg_states,       ARM11_REGCACHE_COUNT);
 
        if (arm11_regs_arch_type == -1)
                arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
@@ -1971,8 +1971,8 @@ static int arm11_build_reg_cache(target_t *target)
        for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
        {
                reg_t *                                         r       = reg_list                      + i;
-               const arm11_reg_defs_t *        rd      = arm11_reg_defs        + i;
-               arm11_reg_state_t *                     rs      = arm11_reg_states      + i;
+               const struct arm11_reg_defs *   rd      = arm11_reg_defs        + i;
+               struct arm11_reg_state *                        rs      = arm11_reg_states      + i;
 
                r->name                         = rd->name;
                r->size                         = 32;
@@ -2064,7 +2064,7 @@ static const uint32_t arm11_coproc_instruction_limits[] =
        0xFFFFFFFF,             /* value */
 };
 
-static arm11_common_t * arm11_find_target(const char * arg)
+static struct arm11_common * arm11_find_target(const char * arg)
 {
        struct jtag_tap *       tap;
        target_t *              t;
@@ -2099,7 +2099,7 @@ static int arm11_mrc_inner(target_t *target, int cpnum,
                return ERROR_FAIL;
        }
                
-       arm11_common_t * arm11 = target->arch_info;
+       struct arm11_common * arm11 = target->arch_info;
 
        uint32_t instr = 0xEE000010     |
                (cpnum <<  8) |
@@ -2151,7 +2151,7 @@ static COMMAND_HELPER(arm11_handle_etm_read_write, bool read)
                return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
-       arm11_common_t * arm11 = arm11_find_target(args[0]);
+       struct arm11_common * arm11 = arm11_find_target(args[0]);
 
        if (!arm11)
        {
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1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)