ARM11: use shared DSCR bit names

[openocd.git] / src / target / arm11.h

diff --git a/src/target/arm11.h b/src/target/arm11.h
index 1cc09e1450cfe53c6d48a6248c72831944c08029..5f78db5dfab966b81cf5782edff0d0081291b1f9 100644 (file)
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -23,10 +23,8 @@
 #ifndef ARM11_H
 #define ARM11_H
 
-#include "armv4_5.h"
-#include "arm_dpm.h"
-
-#define ARM11_REGCACHE_COUNT           1
+#include <target/armv4_5.h>
+#include <target/arm_dpm.h>
 
 #define ARM11_TAP_DEFAULT                      TAP_INVALID
 
@@ -40,6 +38,7 @@
                }                               \
        } while (0)
 
+/* bits from ARMv7 DIDR */
 enum arm11_debug_version
 {
        ARM11_DEBUG_V6                  = 0x01,
@@ -69,18 +68,6 @@ struct arm11_common
 
        bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
 
-       /** \name Shadow registers to save debug state */
-       /*@{*/
-
-       struct reg *    reg_list;                                                       /**< target register list */
-       uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
-
-       /*@}*/
-
-
-       // GA
-       struct reg_cache *core_cache;
-
        struct arm_jtag jtag_info;
 };
 
@@ -109,8 +96,6 @@ enum arm11_instructions
 
 enum arm11_dscr
 {
-       ARM11_DSCR_CORE_HALTED                                                                  = 1 << 0,
-       ARM11_DSCR_CORE_RESTARTED                                                               = 1 << 1,
 
        ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK                                   = 0x0F << 2,
        ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT                                   = 0x00 << 2,
@@ -119,20 +104,6 @@ enum arm11_dscr
        ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION               = 0x03 << 2,
        ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ                                 = 0x04 << 2,
        ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH                   = 0x05 << 2,
-
-       ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                                    = 1 << 6,
-       ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT                                  = 1 << 7,
-       ARM11_DSCR_INTERRUPTS_DISABLE                                                   = 1 << 11,
-       ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE                               = 1 << 13,
-       ARM11_DSCR_MODE_SELECT                                                                  = 1 << 14,
-       ARM11_DSCR_WDTR_FULL                                                                    = 1 << 29,
-       ARM11_DSCR_RDTR_FULL                                                                    = 1 << 30,
-};
-
-enum arm11_cpsr
-{
-       ARM11_CPSR_T                            = 1 << 5,
-       ARM11_CPSR_J                            = 1 << 24,
 };
 
 enum arm11_sc7
@@ -146,10 +117,4 @@ enum arm11_sc7
        ARM11_SC7_WCR0                          = 112,
 };
 
-struct arm11_reg_state
-{
-       uint32_t                                def_index;
-       struct target *                 target;
-};
-
 #endif /* ARM11_H */