#ifndef ARM11_H
#define ARM11_H
-#include "armv4_5.h"
-#include "arm_dpm.h"
-
-#define ARM11_REGCACHE_COUNT 3
+#include <target/armv4_5.h>
+#include <target/arm_dpm.h>
#define ARM11_TAP_DEFAULT TAP_INVALID
} \
} while (0)
+/* bits from ARMv7 DIDR */
enum arm11_debug_version
{
ARM11_DEBUG_V6 = 0x01,
size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
size_t free_brps; /**< Number of breakpoints allocated */
- uint32_t last_dscr; /**< Last retrieved DSCR value;
- Use only for debug message generation */
-
- bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
-
- /** \name Shadow registers to save debug state */
- /*@{*/
+ uint32_t dscr; /**< Last retrieved DSCR value. */
- struct reg * reg_list; /**< target register list */
- uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
+ uint32_t saved_rdtr;
+ uint32_t saved_wdtr;
- /*@}*/
+ bool is_rdtr_saved;
+ bool is_wdtr_saved;
-
- // GA
- struct reg_cache *core_cache;
+ bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
struct arm_jtag jtag_info;
};
enum arm11_dscr
{
- ARM11_DSCR_CORE_HALTED = 1 << 0,
- ARM11_DSCR_CORE_RESTARTED = 1 << 1,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
-
- ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
- ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
- ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
- ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
- ARM11_DSCR_MODE_SELECT = 1 << 14,
- ARM11_DSCR_WDTR_FULL = 1 << 29,
- ARM11_DSCR_RDTR_FULL = 1 << 30,
-};
-
-enum arm11_cpsr
-{
- ARM11_CPSR_T = 1 << 5,
- ARM11_CPSR_J = 1 << 24,
};
enum arm11_sc7
ARM11_SC7_WCR0 = 112,
};
-struct arm11_reg_state
-{
- uint32_t def_index;
- struct target * target;
-};
-
#endif /* ARM11_H */