#include "arm_jtag.h"
#include "arm11_dbgtap.h"
-#include "time_support.h"
+#include <helper/time_support.h>
#if 0
-#define JTAG_DEBUG(expr ...) DEBUG(expr)
+#define JTAG_DEBUG(expr ...) do { if (1) LOG_DEBUG(expr); } while (0)
#else
-#define JTAG_DEBUG(expr ...) do {} while (0)
+#define JTAG_DEBUG(expr ...) do { if (0) LOG_DEBUG(expr); } while (0)
#endif
/*
*/
void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field)
{
- field->tap = arm11->target->tap;
+ field->tap = arm11->arm.target->tap;
field->num_bits = num_bits;
field->out_value = out_data;
field->in_value = in_data;
*/
void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
{
- struct jtag_tap *tap;
- tap = arm11->target->tap;
+ struct jtag_tap *tap = arm11->arm.target->tap;
if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
{
static void arm11_add_debug_INST(struct arm11_common * arm11,
uint32_t inst, uint8_t * flag, tap_state_t state)
{
- JTAG_DEBUG("INST <= 0x%08x", inst);
+ JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst);
struct scan_field itr[2];
arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
}
-/** Read the Debug Status and Control Register (DSCR)
- *
- * same as CP14 c1
+/**
+ * Read and save the Debug Status and Control Register (DSCR).
*
* \param arm11 Target state variable.
- * \param value DSCR content
- * \return Error status
+ * \return Error status; arm11->dscr is updated on success.
*
- * \remarks This is a stand-alone function that executes the JTAG command queue.
+ * \remarks This is a stand-alone function that executes the JTAG
+ * command queue. It does not require the ARM11 debug TAP to be
+ * in any particular state.
*/
-int arm11_read_DSCR(struct arm11_common * arm11, uint32_t *value)
+int arm11_read_DSCR(struct arm11_common *arm11)
{
int retval;
+
retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
if (retval != ERROR_OK)
return retval;
CHECK_RETVAL(jtag_execute_queue());
- if (arm11->last_dscr != dscr)
- JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
-
- arm11->last_dscr = dscr;
+ if (arm11->dscr != dscr)
+ JTAG_DEBUG("DSCR = %08x (OLD %08x)",
+ (unsigned) dscr,
+ (unsigned) arm11->dscr);
- *value = dscr;
+ arm11->dscr = dscr;
return ERROR_OK;
}
CHECK_RETVAL(jtag_execute_queue());
- JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
+ JTAG_DEBUG("DSCR <= %08x (OLD %08x)",
+ (unsigned) dscr,
+ (unsigned) arm11->dscr);
- arm11->last_dscr = dscr;
+ arm11->dscr = dscr;
return ERROR_OK;
}
-
-
-/** Get the debug reason from Debug Status and Control Register (DSCR)
- *
- * \param dscr DSCR value to analyze
- * \return Debug reason
- *
- */
-enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr)
-{
- switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
- {
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
- LOG_INFO("Debug entry: JTAG HALT");
- return DBG_REASON_DBGRQ;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
- LOG_INFO("Debug entry: breakpoint");
- return DBG_REASON_BREAKPOINT;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
- LOG_INFO("Debug entry: watchpoint");
- return DBG_REASON_WATCHPOINT;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
- LOG_INFO("Debug entry: BKPT instruction");
- return DBG_REASON_BREAKPOINT;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
- LOG_INFO("Debug entry: EDBGRQ signal");
- return DBG_REASON_DBGRQ;
-
- case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
- LOG_INFO("Debug entry: VCR vector catch");
- return DBG_REASON_BREAKPOINT;
-
- default:
- LOG_INFO("Debug entry: unknown");
- return DBG_REASON_DBGRQ;
- }
-};
-
-
-
/** Prepare the stage for ITR/DTR operations
* from the arm11_run_instr... group of functions.
*
CHECK_RETVAL(jtag_execute_queue());
- JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
+ JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
+ (unsigned) Data, Ready, nRetry);
long long then = 0;
CHECK_RETVAL(jtag_execute_queue());
- JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
+ JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
+ (unsigned) Data, Ready, nRetry);
long long then = 0;
do
{
- JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
+ JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d",
+ (unsigned) AddressOut,
+ (unsigned) DataOut,
+ nRW);
- arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields), chain7_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields),
+ chain7_fields, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
- JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
+ JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d",
+ (unsigned) AddressIn,
+ (unsigned) DataIn,
+ Ready);
}
while (!Ready); /* 'nRW' is 'Ready' on read out */
for (size_t i = 0; i < count; i++)
{
- JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
+ JTAG_DEBUG("SC7 %02d: %02x %s %08x",
+ (unsigned) i, actions[i].address,
+ actions[i].write ? "<=" : "=>",
+ (unsigned) actions[i].value);
}
return ERROR_OK;
return arm11_run_instr_data_finish(arm11);
}
+
+/************************************************************************/
+
+/*
+ * ARM11 provider for the OpenOCD implementation of the standard
+ * architectural ARM v6/v7 "Debug Programmer's Model" (DPM).
+ */
+
+static inline struct arm11_common *dpm_to_arm11(struct arm_dpm *dpm)
+{
+ return container_of(dpm, struct arm11_common, dpm);
+}
+
+static int arm11_dpm_prepare(struct arm_dpm *dpm)
+{
+ struct arm11_common *arm11 = dpm_to_arm11(dpm);
+
+ arm11 = container_of(dpm->arm, struct arm11_common, arm);
+
+ return arm11_run_instr_data_prepare(dpm_to_arm11(dpm));
+}
+
+static int arm11_dpm_finish(struct arm_dpm *dpm)
+{
+ return arm11_run_instr_data_finish(dpm_to_arm11(dpm));
+}
+
+static int arm11_dpm_instr_write_data_dcc(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t data)
+{
+ return arm11_run_instr_data_to_core(dpm_to_arm11(dpm),
+ opcode, &data, 1);
+}
+
+static int arm11_dpm_instr_write_data_r0(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t data)
+{
+ return arm11_run_instr_data_to_core_via_r0(dpm_to_arm11(dpm),
+ opcode, data);
+}
+
+static int arm11_dpm_instr_read_data_dcc(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t *data)
+{
+ return arm11_run_instr_data_from_core(dpm_to_arm11(dpm),
+ opcode, data, 1);
+}
+
+static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t *data)
+{
+ return arm11_run_instr_data_from_core_via_r0(dpm_to_arm11(dpm),
+ opcode, data);
+}
+
+/** Set up high-level debug module utilities */
+int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
+{
+ struct arm_dpm *dpm = &arm11->dpm;
+ int retval;
+
+ dpm->arm = &arm11->arm;
+
+ dpm->didr = didr;
+
+ dpm->prepare = arm11_dpm_prepare;
+ dpm->finish = arm11_dpm_finish;
+
+ dpm->instr_write_data_dcc = arm11_dpm_instr_write_data_dcc;
+ dpm->instr_write_data_r0 = arm11_dpm_instr_write_data_r0;
+
+ dpm->instr_read_data_dcc = arm11_dpm_instr_read_data_dcc;
+ dpm->instr_read_data_r0 = arm11_dpm_instr_read_data_r0;
+
+ retval = arm_dpm_setup(dpm);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = arm_dpm_initialize(dpm);
+
+ return retval;
+}
Code Review / openocd.git / blobdiff