* Copyright (C) 2008 digenius technology GmbH. *
* Michael Bruck *
* *
- * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
+ * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
#include "config.h"
#endif
-#include "arm11.h"
+#include "arm11_dbgtap.h"
+#include "time_support.h"
#if 0
#define JTAG_DEBUG(expr ...) DEBUG(expr)
#else
-#define JTAG_DEBUG(expr ...) do {} while(0)
+#define JTAG_DEBUG(expr ...) do {} while (0)
#endif
/*
Conversely there may be other places in this code where the ARM11 code relies
on the driver to hit through RTI when coming from Update-?R.
*/
-tap_state_t arm11_move_pi_to_si_via_ci[] =
+static const tap_state_t arm11_move_pi_to_si_via_ci[] =
{
TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
};
return ERROR_OK;
}
-tap_state_t arm11_move_pd_to_sd_via_cd[] =
+static const tap_state_t arm11_move_pd_to_sd_via_cd[] =
{
TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
* \param arm11 Target state variable.
* \param num_bits Length of the data field
* \param out_data pointer to the data that will be sent out
- * <em>(data is read when it is added to the JTAG queue)</em>
+ * <em > (data is read when it is added to the JTAG queue)</em>
* \param in_data pointer to the memory that will receive data that was clocked in
- * <em>(data is written when the JTAG queue is executed)</em>
+ * <em > (data is written when the JTAG queue is executed)</em>
* \param field target data structure that will be initialized
*/
void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state)
+int arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state)
{
JTAG_DEBUG("SCREG <= 0x%02x", chain);
jtag_execute_queue_noclear();
arm11_in_handler_SCAN_N(tmp);
+
+ return jtag_execute_queue();
}
/** Write an instruction into the ITR register
*/
int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value)
{
- arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
+ int retval;
+ retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
+ if (retval != ERROR_OK)
+ return retval;
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
arm11->last_dscr = dscr;
- *value=dscr;
+ *value = dscr;
return ERROR_OK;
}
*/
int arm11_write_DSCR(arm11_common_t * arm11, uint32_t dscr)
{
- arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
+ int retval;
+ retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
+ if (retval != ERROR_OK)
+ return retval;
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
* \param arm11 Target state variable.
*
*/
-void arm11_run_instr_data_prepare(arm11_common_t * arm11)
+int arm11_run_instr_data_prepare(arm11_common_t * arm11)
{
- arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
+ return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
}
/** Cleanup after ITR/DTR operations
* \param arm11 Target state variable.
*
*/
-void arm11_run_instr_data_finish(arm11_common_t * arm11)
+int arm11_run_instr_data_finish(arm11_common_t * arm11)
{
- arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
+ return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
}
+
/** Execute one or multiple instructions via ITR
*
* \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
{
arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
+ int i = 0;
while (1)
{
uint8_t flag;
if (flag)
break;
+
+ long long then = 0;
+
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+
+ i++;
}
}
* \param opcode ARM opcode
*
*/
-void arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode)
+int arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode)
{
- arm11_run_instr_no_data(arm11, &opcode, 1);
+ return arm11_run_instr_no_data(arm11, &opcode, 1);
}
while (count--)
{
+ int i = 0;
do
{
Data = *data;
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
+
+ long long then = 0;
+
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+
+ i++;
}
while (!Ready);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+ int i = 0;
do
{
Data = 0;
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
+
+ long long then = 0;
+
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+
+ i++;
}
while (!Ready);
*
* To disable this code, try "memwrite burst false"
*
+ * FIX!!! should we use multiple TAP_IDLE here or not???
+ *
+ * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
+ * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
*/
-tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
+static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
{
TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
- uint8_t Readies[count + 1];
+ uint8_t *Readies;
+ size_t readiesNum = (count + 1);
+ size_t bytes = sizeof(*Readies)*readiesNum;
+ Readies = (uint8_t *) malloc(bytes);
+ if (Readies == NULL)
+ {
+ LOG_ERROR("Out of memory allocating " ZU " bytes", bytes);
+ return ERROR_FAIL;
+ }
+
uint8_t * ReadyPos = Readies;
while (count--)
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- CHECK_RETVAL(jtag_execute_queue());
-
- size_t error_count = 0;
-
- for (size_t i = 0; i < asizeof(Readies); i++)
+ int retval = jtag_execute_queue();
+ if (retval == ERROR_OK)
{
- if (Readies[i] != 1)
+ size_t error_count = 0;
+
+ for (size_t i = 0; i < readiesNum; i++)
{
- error_count++;
+ if (Readies[i] != 1)
+ {
+ error_count++;
+ }
}
+
+ if (error_count > 0 )
+ LOG_ERROR(ZU " words out of " ZU " not transferred", error_count, readiesNum);
+
}
- if (error_count)
- LOG_ERROR("Transfer errors " ZU, error_count);
+ free(Readies);
- return ERROR_OK;
+ return retval;
}
while (count--)
{
+ int i = 0;
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
+
+ long long then = 0;
+
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+
+ i++;
}
while (!Ready);
* \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
*
*/
-void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t * data)
+int arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t * data)
{
- arm11_run_instr_no_data1(arm11, opcode);
+ int retval;
+ retval = arm11_run_instr_no_data1(arm11, opcode);
+ if (retval != ERROR_OK)
+ return retval;
/* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
+
+ return ERROR_OK;
}
/** Load data into core via DTR then move it to r0 then
* \param data Data word that will be written to r0 before \p opcode is executed
*
*/
-void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
+int arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
{
+ int retval;
/* MRC p14,0,r0,c0,c5,0 */
- arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
+ retval = arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
+ if (retval != ERROR_OK)
+ return retval;
- arm11_run_instr_no_data1(arm11, opcode);
+ retval = arm11_run_instr_no_data1(arm11, opcode);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
}
/** Apply reads and writes to scan chain 7
*/
int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
{
- arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
+ int retval;
+
+ retval = arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
+ if (retval != ERROR_OK)
+ return retval;
arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
*/
int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result)
{
- arm11_run_instr_data_prepare(arm11);
+ int retval;
+ retval = arm11_run_instr_data_prepare(arm11);
+ if (retval != ERROR_OK)
+ return retval;
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
- arm11_run_instr_data_finish(arm11);
+ return arm11_run_instr_data_finish(arm11);
+}
+
+
+/** Write Embedded Trace Macrocell (ETM) via Scan chain 6
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
+ *
+ * \param arm11 Target state variable.
+ * \param address 7 bit ETM register address
+ * \param value Value to be written
+ *
+ * \return Error status
+ *
+ * \remarks This is a stand-alone function that executes the JTAG command queue.
+ */
+int arm11_write_etm(arm11_common_t * arm11, uint8_t address, uint32_t value)
+{
+ CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
+
+ /* Uses INTEST for read and write */
+ arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+
+ scan_field_t chain6_fields[3];
+
+ uint8_t nRW = 1;
+
+ arm11_setup_field(arm11, 32, &value, NULL, chain6_fields + 0);
+ arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
+ arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+
+ arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+ CHECK_RETVAL(jtag_execute_queue());
return ERROR_OK;
}
+/** Read Embedded Trace Macrocell (ETM) via Scan chain 6
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
+ *
+ * \param arm11 Target state variable.
+ * \param address 7 bit ETM register address
+ * \param value Pointer that receives value that was read
+ *
+ * \return Error status
+ *
+ * \remarks This is a stand-alone function that executes the JTAG command queue.
+ */
+int arm11_read_etm(arm11_common_t * arm11, uint8_t address, uint32_t * value)
+{
+ CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
+
+ /* Uses INTEST for read and write */
+ arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+
+ scan_field_t chain6_fields[3];
+
+ uint8_t nRW = 0;
+
+ arm11_setup_field(arm11, 32, NULL, NULL, chain6_fields + 0);
+ arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
+ arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+
+ arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+ /* Data is made available in Capture-DR and shifted out on the next access */
+
+ arm11_setup_field(arm11, 32, NULL, value, chain6_fields + 0);
+ arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
+ arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+
+ arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+ CHECK_RETVAL(jtag_execute_queue());
+
+ return ERROR_OK;
+}
Code Review / openocd.git / blobdiff