dsp5680xx - separate debug from halt

[openocd.git] / src / target / arm720t.c

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 6bf38bbc76bdabce06729a8028db49328bc547cd..b41fbeccc5598b0d033e8d125b76264d09d3bad5 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -202,13 +202,18 @@ static int arm720t_enable_mmu_caches(struct target *target,
        return retval;
 }
 
-static void arm720t_post_debug_entry(struct target *target)
+static int arm720t_post_debug_entry(struct target *target)
 {
        struct arm720t_common *arm720t = target_to_arm720(target);
+       int retval;
 
        /* examine cp15 control reg */
-       arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
-       jtag_execute_queue();
+       retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
        arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
@@ -216,9 +221,14 @@ static void arm720t_post_debug_entry(struct target *target)
        arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
        /* save i/d fault status and address register */
-       arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
-       arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
-       jtag_execute_queue();
+       retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       return retval;
 }
 
 static void arm720t_pre_restore_context(struct target *target)
@@ -243,15 +253,12 @@ static int arm720t_verify_pointer(struct command_context *cmd_ctx,
 static int arm720t_arch_state(struct target *target)
 {
        struct arm720t_common *arm720t = target_to_arm720(target);
-       struct arm *armv4_5;
 
        static const char *state[] =
        {
                "disabled", "enabled"
        };
 
-       armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
-
        arm_arch_state(target);
        LOG_USER("MMU: %s, Cache: %s",
                         state[arm720t->armv4_5_mmu.mmu_enabled],
@@ -320,7 +327,7 @@ static int arm720t_read_phys_memory(struct target *target,
 }
 
 static int arm720t_write_phys_memory(struct target *target,
-               uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+               uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        struct arm720t_common *arm720t = target_to_arm720(target);
 
@@ -456,13 +463,11 @@ COMMAND_HANDLER(arm720t_handle_cp15_command)
        int retval;
        struct target *target = get_current_target(CMD_CTX);
        struct arm720t_common *arm720t = target_to_arm720(target);
-       struct arm_jtag *jtag_info;
 
        retval = arm720t_verify_pointer(CMD_CTX, arm720t);
        if (retval != ERROR_OK)
                return retval;
 
-       jtag_info = &arm720t->arm7_9_common.jtag_info;
 
        if (target->state != TARGET_HALTED)
        {