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- Fixes '=' whitespace
[openocd.git] / src / target / arm720t.c
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index b04a17f7eb1b2c72b4bbf4f47c7662ca5986b42e..efca08ddab91bd27d5d2a765ef6ddcc5667036bc 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -22,12 +22,9 @@
 #endif
 
 #include "arm720t.h"
-#include "jtag.h"
-#include "log.h"
 #include "time_support.h"
+#include "target_type.h"
 
-#include <stdlib.h>
-#include <string.h>
 
 #if 0
 #define _DEBUG_INSTRUCTION_EXECUTION_
@@ -46,8 +43,8 @@ int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm720t_quit(void);
 int arm720t_arch_state(struct target_s *target);
-int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
+int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 int arm720t_soft_reset_halt(struct target_s *target);
 
 target_type_t arm720t_target =
@@ -87,24 +84,24 @@ target_type_t arm720t_target =
        .quit = arm720t_quit
 };
 
-int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
+int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruction, int clock)
 {
        int retval = ERROR_OK;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
        scan_field_t fields[2];
-       u8 out_buf[4];
-       u8 instruction_buf = instruction;
+       uint8_t out_buf[4];
+       uint8_t instruction_buf = instruction;
 
        buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 
-       jtag_add_end_state(TAP_DRPAUSE);
-       if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+       jtag_set_end_state(TAP_DRPAUSE);
+       if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
        {
                return retval;
        }
-       if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
+       if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
        {
                return retval;
        }
@@ -121,20 +118,19 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
 
        if (in)
        {
-               u8 tmp[4];
-               fields[1].in_value = tmp;
-               jtag_add_dr_scan_now(2, fields, TAP_INVALID);
-               *in=flip_u32(le_to_h_u32(tmp), 32);
+               fields[1].in_value = (uint8_t *)in;
+               jtag_add_dr_scan(2, fields, jtag_get_end_state());
+               jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
        } else
        {
-               jtag_add_dr_scan(2, fields, TAP_INVALID);
+               jtag_add_dr_scan(2, fields, jtag_get_end_state());
        }
 
        if (clock)
-               jtag_add_runtest(0, TAP_INVALID);
+               jtag_add_runtest(0, jtag_get_end_state());
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-       if((retval = jtag_execute_queue()) != ERROR_OK)
+       if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
                return retval;
        }
@@ -144,13 +140,13 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
        else
                LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 #else
-               LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
+               LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
 #endif
 
        return ERROR_OK;
 }
 
-int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
+int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value)
 {
        /* fetch CP15 opcode */
        arm720t_scan_cp15(target, opcode, NULL, 1, 1);
@@ -167,7 +163,7 @@ int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
        return ERROR_OK;
 }
 
-int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
+int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value)
 {
        /* fetch CP15 opcode */
        arm720t_scan_cp15(target, opcode, NULL, 1, 1);
@@ -183,9 +179,9 @@ int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
        return ERROR_OK;
 }
 
-u32 arm720t_get_ttb(target_t *target)
+uint32_t arm720t_get_ttb(target_t *target)
 {
-       u32 ttb = 0x0;
+       uint32_t ttb = 0x0;
 
        arm720t_read_cp15(target, 0xee120f10, &ttb);
        jtag_execute_queue();
@@ -197,7 +193,7 @@ u32 arm720t_get_ttb(target_t *target)
 
 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 {
-       u32 cp15_control;
+       uint32_t cp15_control;
 
        /* read cp15 control register */
        arm720t_read_cp15(target, 0xee110f10, &cp15_control);
@@ -214,7 +210,7 @@ void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_
 
 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 {
-       u32 cp15_control;
+       uint32_t cp15_control;
 
        /* read cp15 control register */
        arm720t_read_cp15(target, 0xee110f10, &cp15_control);
@@ -239,7 +235,7 @@ void arm720t_post_debug_entry(target_t *target)
        /* examine cp15 control reg */
        arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
        jtag_execute_queue();
-       LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
+       LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
        arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
        arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
@@ -320,7 +316,7 @@ int arm720t_arch_state(struct target_s *target)
        }
 
        LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-                       "cpsr: 0x%8.8x pc: 0x%8.8x\n"
+                       "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
                        "MMU: %s, Cache: %s",
                         armv4_5_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
@@ -333,7 +329,7 @@ int arm720t_arch_state(struct target_s *target)
        return ERROR_OK;
 }
 
-int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -353,7 +349,7 @@ int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 coun
        return retval;
 }
 
-int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
        int retval;
 
@@ -377,9 +373,9 @@ int arm720t_soft_reset_halt(struct target_s *target)
                return retval;
        }
 
-       long long then=timeval_ms();
+       long long then = timeval_ms();
        int timeout;
-       while (!(timeout=((timeval_ms()-then)>1000)))
+       while (!(timeout = ((timeval_ms()-then)>1000)))
        {
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
                {
@@ -392,7 +388,7 @@ int arm720t_soft_reset_halt(struct target_s *target)
                {
                        break;
                }
-               if (debug_level>=3)
+               if (debug_level >= 3)
                {
                        alive_sleep(100);
                } else
@@ -531,14 +527,14 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
        /* one or more argument, access a single register (write if second argument is given */
        if (argc >= 1)
        {
-               u32 opcode = strtoul(args[0], NULL, 0);
+               uint32_t opcode = strtoul(args[0], NULL, 0);
 
                if (argc == 1)
                {
-                       u32 value;
+                       uint32_t value;
                        if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
                        {
-                               command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
+                               command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
                                return ERROR_OK;
                        }
 
@@ -547,17 +543,17 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
                                return retval;
                        }
 
-                       command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
+                       command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
                }
                else if (argc == 2)
                {
-                       u32 value = strtoul(args[1], NULL, 0);
+                       uint32_t value = strtoul(args[1], NULL, 0);
                        if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
                        {
-                               command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
+                               command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
                                return ERROR_OK;
                        }
-                       command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
+                       command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
                }
        }
 
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