else
{
LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
- exit(-1);
+ return ERROR_FAIL;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
- exit(-1);
+ return ERROR_FAIL;
};
return ERROR_OK;
return ERROR_OK;
}
+/*
+ Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
+ in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
+ while the core is held in reset(SRST). It isn't possible to program the halt
+ condition once reset was asserted, hence a hook that allows the target to set
+ up its reset-halt condition prior to asserting reset.
+*/
+
int arm7_9_assert_reset(target_t *target)
{
- int retval;
-
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
- if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
+ if (!(jtag_reset_config & RESET_HAS_SRST))
{
- /* if the target wasn't running, there might be working areas allocated */
- target_free_all_working_areas(target);
+ LOG_ERROR("Can't assert SRST");
+ return ERROR_FAIL;
+ }
+
+ if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
+ {
+ reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
- /* assert SRST and TRST */
- /* system would get ouf sync if we didn't reset test-logic, too */
- if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
+ /* program EmbeddedICE Debug Control Register to deassert DBGRQ
+ * i.e. resume.
+ */
+ buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
+ embeddedice_store_reg(dbg_ctrl);
+
+ /*
+ * Some targets do not support communication while SRST is asserted. We need to
+ * set up the reset vector catch here.
+ *
+ * If TRST is asserted, then these settings will be reset anyway, so setting them
+ * here is harmless.
+ */
+ if (arm7_9->has_vector_catch)
{
- if (retval == ERROR_JTAG_RESET_CANT_SRST)
- {
- return retval;
- }
- else
- {
- LOG_ERROR("unknown error");
- exit(-1);
- }
+ /* program vector catch register to catch reset vector */
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
}
- jtag_add_sleep(5000);
- if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
+ else
{
- if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
- {
- retval = jtag_add_reset(1, 1);
- }
+ /* program watchpoint unit to match on reset vector address */
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
}
}
- else
+
+ /* here we should issue a srst only, but we may have to assert trst as well */
+ if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{
- if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
- {
- if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
- {
- retval = jtag_add_reset(1, 1);
- }
-
- if (retval == ERROR_JTAG_RESET_CANT_SRST)
- {
- return retval;
- }
- else if (retval != ERROR_OK)
- {
- LOG_ERROR("unknown error");
- exit(-1);
- }
- }
+ jtag_add_reset(1, 1);
+ } else
+ {
+ jtag_add_reset(0, 1);
}
+
target->state = TARGET_RESET;
jtag_add_sleep(50000);
-
+
armv4_5_invalidate_core_regs(target);
return ERROR_OK;
return ERROR_OK;
}
-int arm7_9_prepare_reset_halt(target_t *target)
-{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
- /* poll the target, and resume if it was currently halted */
- arm7_9_poll(target);
- if (target->state == TARGET_HALTED)
- {
- arm7_9_resume(target, 1, 0x0, 0, 1);
- }
-
- if (arm7_9->has_vector_catch)
- {
- /* program vector catch register to catch reset vector */
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
- }
- else
- {
- /* program watchpoint unit to match on reset vector address */
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
- }
-
- return ERROR_OK;
-}
-
int arm7_9_halt(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
if (target->state == TARGET_HALTED)
{
- LOG_WARNING("target was already halted");
+ LOG_DEBUG("target was already halted");
return ERROR_OK;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
- LOG_ERROR("JTAG failure");
- exit(-1);
+ return retval;
}
return ERROR_OK;
}
arm_jtag_set_instr(jtag_info, 0x4, NULL);
jtag_add_runtest(1, TAP_RTI);
- if ((jtag_execute_queue()) != ERROR_OK)
- {
- exit(-1);
- }
-
- return ERROR_OK;
+ return jtag_execute_queue();
}
void arm7_9_enable_watchpoints(struct target_s *target)
else
{
LOG_ERROR("unhandled core state");
- exit(-1);
+ return ERROR_FAIL;
}
buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
else
{
LOG_ERROR("unhandled core state");
- exit(-1);
+ return ERROR_FAIL;
}
/* deassert DBGACK and INTDIS */
else
{
LOG_ERROR("unhandled core state");
- exit(-1);
+ return ERROR_FAIL;
}
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
- LOG_ERROR("JTAG failure");
- exit(-1);
+ return retval;
}
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
Code Review / openocd.git / blobdiff