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Edgar Grimberg fixes some memory handling issues and
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 0c63d9209aed41d95cf42a78b1fad80731d85639..249d8d4c1cd160d41ec939742d95b8e314a31055 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -685,7 +685,7 @@ int arm7_9_poll(target_t *target)
        
        if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
        {
-               LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
+/*             LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
                if (target->state == TARGET_UNKNOWN)
                {
                        target->state = TARGET_RUNNING;
@@ -903,6 +903,9 @@ int arm7_9_soft_reset_halt(struct target_s *target)
        
        armv4_5->core_mode = ARMV4_5_MODE_SVC;
        armv4_5->core_state = ARMV4_5_STATE_ARM;
+
+       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+               return ERROR_FAIL;
        
        /* reset registers */
        for (i = 0; i <= 14; i++)
@@ -1009,15 +1012,7 @@ int arm7_9_debug_entry(target_t *target)
        
        if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
-               switch (retval)
-               {
-                       case ERROR_JTAG_QUEUE_FAILED:
-                               LOG_ERROR("JTAG queue failed while writing EmbeddedICE control register");
-                               exit(-1);
-                               break;
-                       default:
-                               break;
-               }
+               return retval;
        }
 
        if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
@@ -1099,6 +1094,8 @@ int arm7_9_debug_entry(target_t *target)
                LOG_ERROR("unknown debug reason: %i", target->debug_reason);
        }
 
+       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+               return ERROR_FAIL;
        
        for (i=0; i<=15; i++)
        {
@@ -1109,9 +1106,12 @@ int arm7_9_debug_entry(target_t *target)
        }
        
        LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
+       
+       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+               return ERROR_FAIL;
 
        /* exceptions other than USR & SYS have a saved program status register */
-       if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
+       if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
        {
                u32 spsr;
                arm7_9->read_xpsr(target, &spsr, 1);
@@ -1148,6 +1148,9 @@ int arm7_9_full_context(target_t *target)
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
+       
+       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+               return ERROR_FAIL;
 
        /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
         * SYS shares registers with User, so we don't touch SYS
@@ -1234,6 +1237,9 @@ int arm7_9_restore_context(target_t *target)
        if (arm7_9->pre_restore_context)
                arm7_9->pre_restore_context(target);
        
+       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+               return ERROR_FAIL;
+               
        /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
         * SYS shares registers with User, so we don't touch SYS
         */
@@ -1643,6 +1649,10 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+       
+       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+               return ERROR_FAIL;
+       
        enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
        
        if ((num < 0) || (num > 16))
@@ -1704,6 +1714,10 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
        u32 reg[16];
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+       
+       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+               return ERROR_FAIL;
+       
        enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
 
        if ((num < 0) || (num > 16))
@@ -1879,6 +1893,9 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
                        break;
        }
        
+       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+               return ERROR_FAIL;
+
        for (i=0; i<=last_reg; i++)
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
 
@@ -2046,6 +2063,9 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
        buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
        embeddedice_store_reg(dbg_ctrl);
        
+       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+               return ERROR_FAIL;
+
        for (i=0; i<=last_reg; i++)
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
 
@@ -2068,6 +2088,12 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
        return ERROR_OK;
 }
 
+static const u32 dcc_code[] = 
+{
+       /* MRC      TST         BNE         MRC         STR         B */
+       0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
+};
+
 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2078,12 +2104,6 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
        u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
        int i;
        
-       u32 dcc_code[] = 
-       {
-               /* MRC      TST         BNE         MRC         STR         B */
-               0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
-       };
-       
        if (!arm7_9->dcc_downloads)
                return target->type->write_memory(target, address, 4, count, buffer);
 
@@ -2624,8 +2644,8 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
        
        arm7_9->dcc_working_area = NULL;
        
-       arm7_9->fast_memory_access = 0;
-       arm7_9->dcc_downloads = 0;
+       arm7_9->fast_memory_access = fast_and_dangerous;
+       arm7_9->dcc_downloads = fast_and_dangerous;
 
        armv4_5->arch_info = arm7_9;
        armv4_5->read_core_reg = arm7_9_read_core_reg;
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