Merge branch 'master' of ssh://dbrownell@openocd.git.sourceforge.net/gitroot/openocd...

[openocd.git] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index e2eb0d5cd4e4fa1bac72e05b0789e336857aed84..2b064f23120301d83a5f51c6accbde5bbfebd363 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -95,7 +95,7 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
        {
                LOG_ERROR("BUG: no hardware comparator available");
        }
-       LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", 
+       LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
                          breakpoint->unique_id,
                          breakpoint->address,
                          breakpoint->set );
@@ -158,7 +158,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
                LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
                return ERROR_FAIL;
        }
-       LOG_DEBUG("SW BP using hw wp: %d", 
+       LOG_DEBUG("SW BP using hw wp: %d",
                          arm7_9->sw_breakpoints_added );
 
        return jtag_execute_queue();
@@ -371,7 +371,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 
        if (breakpoint->type == BKPT_HARD)
        {
-               LOG_DEBUG("BPID: %d Releasing hw wp: %d", 
+               LOG_DEBUG("BPID: %d Releasing hw wp: %d",
                                  breakpoint->unique_id,
                                  breakpoint->set );
                if (breakpoint->set == 1)
@@ -1021,12 +1021,19 @@ int arm7_9_assert_reset(target_t *target)
                return ERROR_FAIL;
        }
 
-       /* at this point trst has been asserted/deasserted once. We want to
-        * program embedded ice while SRST is asserted, but some CPUs gate
-        * the JTAG clock while SRST is asserted
+       /* At this point trst has been asserted/deasserted once. We would
+        * like to program EmbeddedICE while SRST is asserted, instead of
+        * depending on SRST to leave that module alone.  However, many CPUs
+        * gate the JTAG clock while SRST is asserted; or JTAG may need
+        * clock stability guarantees (adaptive clocking might help).
+        *
+        * So we assume JTAG access during SRST is off the menu unless it's
+        * been specifically enabled.
         */
        bool srst_asserted = false;
-       if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) && ((jtag_reset_config & RESET_SRST_GATES_JTAG) == 0))
+
+       if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
+                       && (jtag_reset_config & RESET_SRST_NO_GATING))
        {
                jtag_add_reset(0, 1);
                srst_asserted = true;