* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
arm7_9->wp_available--;
} else
LOG_ERROR("BUG: no hardware comparator available");
- LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
+
+ LOG_DEBUG("BPID: %" PRId32 " (0x%08" TARGET_PRIxADDR ") using hw wp: %d",
breakpoint->unique_id,
breakpoint->address,
breakpoint->set);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
- LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d",
+ LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" TARGET_PRIxADDR ", Type: %d",
breakpoint->unique_id,
breakpoint->address,
breakpoint->type);
if (retval != ERROR_OK)
return retval;
if (verify != arm7_9->arm_bkpt) {
- LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32
+ LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" TARGET_PRIxADDR
" - check that memory is read/writable", breakpoint->address);
return ERROR_OK;
}
if (retval != ERROR_OK)
return retval;
if (verify != arm7_9->thumb_bkpt) {
- LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32
+ LOG_ERROR("Unable to set thumb software breakpoint at address %08" TARGET_PRIxADDR
" - check that memory is read/writable", breakpoint->address);
return ERROR_OK;
}
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
+ LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" TARGET_PRIxADDR,
breakpoint->unique_id,
breakpoint->address);
}
if (breakpoint->type == BKPT_HARD) {
- LOG_DEBUG("BPID: %d Releasing hw wp: %d",
+ LOG_DEBUG("BPID: %" PRId32 " Releasing hw wp: %d",
breakpoint->unique_id,
breakpoint->set);
if (breakpoint->set == 1) {
if (retval != ERROR_OK)
return retval;
current_instr = target_buffer_get_u16(target, (uint8_t *)¤t_instr);
- if (current_instr == arm7_9->thumb_bkpt)
+ if (current_instr == arm7_9->thumb_bkpt) {
retval = target_write_memory(target,
breakpoint->address, 2, 1, breakpoint->orig_instr);
if (retval != ERROR_OK)
return retval;
-
+ }
}
if (--arm7_9->sw_breakpoint_count == 0) {
/* set RESTART instruction */
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, 0xf, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
}
- retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, 0x4, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
- int timeout;
+ int64_t then = timeval_ms();
+ bool timeout;
while (!(timeout = ((timeval_ms()-then) > 1000))) {
/* read debug status register */
embeddedice_read_reg(dbg_stat);
/* set RESTART instruction */
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, 0xf, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
}
- retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, 0x4, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
enum reset_types jtag_reset_config = jtag_get_reset_config();
bool use_event = false;
+ /* TODO: apply hw reset signal in not examined state */
+ if (!(target_was_examined(target))) {
+ LOG_WARNING("Reset is not asserted because the target is not examined.");
+ LOG_WARNING("Use a reset button or power cycle the target.");
+ return ERROR_TARGET_NOT_EXAMINED;
+ }
+
LOG_DEBUG("target->state: %s", target_state_name(target));
if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
cpsr &= ~0xff;
cpsr |= 0xd3;
arm_set_cpsr(arm, cpsr);
- arm->cpsr->dirty = 1;
+ arm->cpsr->dirty = true;
/* start fetching from 0x0 */
buf_set_u32(arm->pc->value, 0, 32, 0x0);
- arm->pc->dirty = 1;
- arm->pc->valid = 1;
+ arm->pc->dirty = true;
+ arm->pc->valid = true;
/* reset registers */
for (i = 0; i <= 14; i++) {
struct reg *r = arm_reg_current(arm, i);
buf_set_u32(r->value, 0, 32, 0xffffffff);
- r->dirty = 1;
- r->valid = 1;
+ r->dirty = true;
+ r->valid = true;
}
retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
buf_set_u32(r->value, 0, 32, context[i]);
/* r0 and r15 (pc) have to be restored later */
r->dirty = (i == 0) || (i == 15);
- r->valid = 1;
+ r->valid = true;
}
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
if (retval != ERROR_OK)
return retval;
buf_set_u32(arm->spsr->value, 0, 32, spsr);
- arm->spsr->dirty = 0;
- arm->spsr->valid = 1;
+ arm->spsr->dirty = false;
+ arm->spsr->valid = true;
}
retval = jtag_execute_queue();
uint32_t mask = 0;
uint32_t *reg_p[16];
int j;
- int valid = 1;
+ bool valid = true;
/* check if there are invalid registers in the current mode
*/
for (j = 0; j <= 16; j++) {
- if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
- valid = 0;
+ if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid)
+ valid = false;
}
if (!valid) {
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
for (j = 0; j < 15; j++) {
- if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
- armv4_5_number_to_mode(i), j).valid == 0) {
+ if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
+ armv4_5_number_to_mode(i), j).valid) {
reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE(
arm->core_cache,
armv4_5_number_to_mode(i),
mask |= 1 << j;
ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5_number_to_mode(i),
- j).valid = 1;
+ j).valid = true;
ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5_number_to_mode(i),
- j).dirty = 0;
+ j).dirty = false;
}
}
arm7_9->read_core_regs(target, mask, reg_p);
/* check if the PSR has to be read */
- if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
- 16).valid == 0) {
+ if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
+ 16).valid) {
arm7_9->read_xpsr(target,
(uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5_number_to_mode(i), 16).value, 1);
ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
- 16).valid = 1;
+ 16).valid = true;
ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
- 16).dirty = 0;
+ 16).dirty = false;
}
}
}
struct reg *reg;
enum arm_mode current_mode = arm->core_mode;
int i, j;
- int dirty;
+ bool dirty;
int mode_change;
LOG_DEBUG("-");
for (i = 0; i < 6; i++) {
LOG_DEBUG("examining %s mode",
arm_mode_name(arm->core_mode));
- dirty = 0;
+ dirty = false;
mode_change = 0;
/* check if there are dirty registers in the current mode
*/
for (j = 0; j <= 16; j++) {
reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j);
- if (reg->dirty == 1) {
- if (reg->valid == 1) {
- dirty = 1;
+ if (reg->dirty) {
+ if (reg->valid) {
+ dirty = true;
LOG_DEBUG("examining dirty reg: %s", reg->name);
struct arm_reg *reg_arch_info;
reg_arch_info = reg->arch_info;
armv4_5_number_to_mode(i),
j);
- if (reg->dirty == 1) {
+ if (reg->dirty) {
regs[j] = buf_get_u32(reg->value, 0, 32);
mask |= 1 << j;
num_regs++;
- reg->dirty = 0;
- reg->valid = 1;
+ reg->dirty = false;
+ reg->valid = true;
LOG_DEBUG("writing register %i mode %s "
"with value 0x%8.8" PRIx32, j,
arm_mode_name(arm->core_mode),
arm7_9->write_xpsr(target,
buf_get_u32(arm->cpsr->value, 0, 32)
& ~0x20, 0);
- arm->cpsr->dirty = 0;
- arm->cpsr->valid = 1;
+ arm->cpsr->dirty = false;
+ arm->cpsr->valid = true;
}
/* restore PC */
LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
buf_get_u32(arm->pc->value, 0, 32));
arm7_9->write_pc(target, buf_get_u32(arm->pc->value, 0, 32));
- arm->pc->dirty = 0;
+ arm->pc->dirty = false;
return ERROR_OK;
}
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, 0xf, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
}
- retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, 0x4, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
int arm7_9_resume(struct target *target,
int current,
- uint32_t address,
+ target_addr_t address,
int handle_breakpoints,
int debug_execution)
{
breakpoint = breakpoint_find(target,
buf_get_u32(arm->pc->value, 0, 32));
if (breakpoint != NULL) {
- LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)",
+ LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR " (id: %" PRId32,
breakpoint->address,
breakpoint->unique_id);
retval = arm7_9_unset_breakpoint(target, breakpoint);
LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
buf_get_u32(arm->pc->value, 0, 32));
- LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
+ LOG_DEBUG("set breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
retval = arm7_9_set_breakpoint(target, breakpoint);
if (retval != ERROR_OK)
return retval;
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
}
-int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
+int arm7_9_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *arm = &arm7_9->arm;
if (retval != ERROR_OK)
return retval;
- r->valid = 1;
- r->dirty = 0;
+ r->valid = true;
+ r->dirty = false;
buf_set_u32(r->value, 0, 32, value);
if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode)
}
static int arm7_9_write_core_reg(struct target *target, struct reg *r,
- int num, enum arm_mode mode, uint32_t value)
+ int num, enum arm_mode mode, uint8_t *value)
{
uint32_t reg[16];
struct arm_reg *areg = r->arch_info;
if ((num >= 0) && (num <= 15)) {
/* write a normal core register */
- reg[num] = value;
+ reg[num] = buf_get_u32(value, 0, 32);
arm7_9->write_core_regs(target, 1 << num, reg);
} else {
*/
int spsr = (areg->mode != ARM_MODE_ANY);
+ uint32_t t = buf_get_u32(value, 0, 32);
/* if we're writing the CPSR, mask the T bit */
if (!spsr)
- value &= ~0x20;
+ t &= ~0x20;
- arm7_9->write_xpsr(target, value, spsr);
+ arm7_9->write_xpsr(target, t, spsr);
}
- r->valid = 1;
- r->dirty = 0;
+ r->valid = true;
+ r->dirty = false;
if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode)
&& (areg->mode != ARM_MODE_ANY)) {
}
int arm7_9_read_memory(struct target *target,
- uint32_t address,
+ target_addr_t address,
uint32_t size,
uint32_t count,
uint8_t *buffer)
int retval;
int last_reg = 0;
- LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
+ LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
address, size, count);
if (target->state != TARGET_HALTED) {
if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) {
LOG_WARNING(
- "memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")",
+ "memory read caused data abort "
+ "(address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")",
address,
size,
count);
}
int arm7_9_write_memory(struct target *target,
- uint32_t address,
+ target_addr_t address,
uint32_t size,
uint32_t count,
const uint8_t *buffer)
if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) {
LOG_WARNING(
- "memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")",
+ "memory write caused data abort "
+ "(address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")",
address,
size,
count);
return ERROR_OK;
}
+int arm7_9_write_memory_opt(struct target *target,
+ target_addr_t address,
+ uint32_t size,
+ uint32_t count,
+ const uint8_t *buffer)
+{
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ int retval;
+
+ if (size == 4 && count > 32 && arm7_9->bulk_write_memory) {
+ /* Attempt to do a bulk write */
+ retval = arm7_9->bulk_write_memory(target, address, count, buffer);
+
+ if (retval == ERROR_OK)
+ return ERROR_OK;
+ }
+
+ return arm7_9->write_memory(target, address, size, count, buffer);
+}
+
+int arm7_9_write_memory_no_opt(struct target *target,
+ uint32_t address,
+ uint32_t size,
+ uint32_t count,
+ const uint8_t *buffer)
+{
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+
+ return arm7_9->write_memory(target, address, size, count, buffer);
+}
+
static int dcc_count;
static const uint8_t *dcc_buffer;
};
int arm7_9_bulk_write_memory(struct target *target,
- uint32_t address,
+ target_addr_t address,
uint32_t count,
const uint8_t *buffer)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- int i;
+
+ if (address % 4 != 0)
+ return ERROR_TARGET_UNALIGNED_ACCESS;
if (!arm7_9->dcc_downloads)
- return target_write_memory(target, address, 4, count, buffer);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
/* regrab previously allocated working_area, or allocate a new one */
if (!arm7_9->dcc_working_area) {
/* make sure we have a working area */
if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK) {
LOG_INFO("no working area available, falling back to memory writes");
- return target_write_memory(target, address, 4, count, buffer);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
/* copy target instructions to target endianness */
- for (i = 0; i < 6; i++)
- target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
+ target_buffer_set_u32_array(target, dcc_code_buf, ARRAY_SIZE(dcc_code), dcc_code);
- /* write DCC code to working area */
- retval = target_write_memory(target,
+ /* write DCC code to working area, using the non-optimized
+ * memory write to avoid ending up here again */
+ retval = arm7_9_write_memory_no_opt(target,
arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
if (retval != ERROR_OK)
return retval;
uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
if (endaddress != (address + count*4)) {
LOG_ERROR(
- "DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "",
+ "DCC write failed, expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32 "",
(address + count*4),
endaddress);
retval = ERROR_FAIL;
return retval;
return target_register_timer_callback(arm7_9_handle_target_request,
- 1, 1, target);
+ 1, TARGET_TIMER_TYPE_PERIODIC, target);
}
static const struct command_registration arm7_9_any_command_handlers[] = {
{
- "dbgrq",
+ .name = "dbgrq",
.handler = handle_arm7_9_dbgrq_command,
.mode = COMMAND_ANY,
.usage = "['enable'|'disable']",
"for target halt requests",
},
{
- "fast_memory_access",
+ .name = "fast_memory_access",
.handler = handle_arm7_9_fast_memory_access_command,
.mode = COMMAND_ANY,
.usage = "['enable'|'disable']",
"but potentially safer accesses",
},
{
- "dcc_downloads",
+ .name = "dcc_downloads",
.handler = handle_arm7_9_dcc_downloads_command,
.mode = COMMAND_ANY,
.usage = "['enable'|'disable']",
Code Review / openocd.git / blobdiff