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ARM: ARMV4_5_COMMON_MAGIC --> ARM_COMMON_MAGIC
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index b4116726258edf7f51e432b57009706e1f4d543d..68005c013855156c142a53ed562508b55c7b457c 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1211,7 +1211,7 @@ int arm7_9_soft_reset_halt(struct target *target)
                uint32_t r0_thumb, pc_thumb;
                LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
                /* Entered debug from Thumb mode */
-               armv4_5->core_state = ARMV4_5_STATE_THUMB;
+               armv4_5->core_state = ARM_STATE_THUMB;
                arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
        }
 
@@ -1373,7 +1373,7 @@ static int arm7_9_debug_entry(struct target *target)
        {
                LOG_DEBUG("target entered debug from Thumb state");
                /* Entered debug from Thumb mode */
-               armv4_5->core_state = ARMV4_5_STATE_THUMB;
+               armv4_5->core_state = ARM_STATE_THUMB;
                cpsr_mask = 1 << 5;
                arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
                LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
@@ -1385,13 +1385,13 @@ static int arm7_9_debug_entry(struct target *target)
                 * B.7.3 for the reverse.  That'd be the bare minimum...
                 */
                LOG_DEBUG("target entered debug from Jazelle state");
-               armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
+               armv4_5->core_state = ARM_STATE_JAZELLE;
                cpsr_mask = 1 << 24;
                LOG_ERROR("Jazelle debug entry -- BROKEN!");
        } else {
                LOG_DEBUG("target entered debug from ARM state");
                /* Entered debug from ARM mode */
-               armv4_5->core_state = ARMV4_5_STATE_ARM;
+               armv4_5->core_state = ARM_STATE_ARM;
        }
 
        for (i = 0; i < 16; i++)
@@ -1419,21 +1419,21 @@ static int arm7_9_debug_entry(struct target *target)
        LOG_DEBUG("target entered debug state in %s mode",
                         arm_mode_name(armv4_5->core_mode));
 
-       if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+       if (armv4_5->core_state == ARM_STATE_THUMB)
        {
                LOG_DEBUG("thumb state, applying fixups");
                context[0] = r0_thumb;
                context[15] = pc_thumb;
-       } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+       } else if (armv4_5->core_state == ARM_STATE_ARM)
        {
                /* adjust value stored by STM */
                context[15] -= 3 * 4;
        }
 
        if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
-               context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
+               context[15] -= 3 * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
        else
-               context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
+               context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2);
 
        for (i = 0; i <= 15; i++)
        {
@@ -1582,7 +1582,7 @@ int arm7_9_restore_context(struct target *target)
        struct arm *armv4_5 = &arm7_9->armv4_5_common;
        struct reg *reg;
        struct arm_reg *reg_arch_info;
-       enum armv4_5_mode current_mode = armv4_5->core_mode;
+       enum arm_mode current_mode = armv4_5->core_mode;
        int i, j;
        int dirty;
        int mode_change;
@@ -1622,10 +1622,10 @@ int arm7_9_restore_context(struct target *target)
                                {
                                        dirty = 1;
                                        LOG_DEBUG("examining dirty reg: %s", reg->name);
-                                       if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
+                                       if ((reg_arch_info->mode != ARM_MODE_ANY)
                                                && (reg_arch_info->mode != current_mode)
-                                               && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
-                                               && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
+                                               && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
+                                               && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR)))
                                        {
                                                mode_change = 1;
                                                LOG_DEBUG("require mode change");
@@ -1684,7 +1684,7 @@ int arm7_9_restore_context(struct target *target)
 
                        reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
                        reg_arch_info = reg->arch_info;
-                       if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
+                       if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
                        {
                                LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
                                arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
@@ -1846,9 +1846,9 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
                                return retval;
                        }
 
-                       if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+                       if (armv4_5->core_state == ARM_STATE_ARM)
                                arm7_9->branch_resume(target);
-                       else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+                       else if (armv4_5->core_state == ARM_STATE_THUMB)
                        {
                                arm7_9->branch_resume_thumb(target);
                        }
@@ -1895,11 +1895,11 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
                return retval;
        }
 
-       if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+       if (armv4_5->core_state == ARM_STATE_ARM)
        {
                arm7_9->branch_resume(target);
        }
-       else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+       else if (armv4_5->core_state == ARM_STATE_THUMB)
        {
                arm7_9->branch_resume_thumb(target);
        }
@@ -2046,11 +2046,11 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
 
        arm7_9->enable_single_step(target, next_pc);
 
-       if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+       if (armv4_5->core_state == ARM_STATE_ARM)
        {
                arm7_9->branch_resume(target);
        }
-       else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+       else if (armv4_5->core_state == ARM_STATE_THUMB)
        {
                arm7_9->branch_resume_thumb(target);
        }
@@ -2093,7 +2093,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
 }
 
 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
-               int num, enum armv4_5_mode mode)
+               int num, enum arm_mode mode)
 {
        uint32_t* reg_p[16];
        uint32_t value;
@@ -2107,9 +2107,9 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))
+                       && (areg->mode != ARM_MODE_ANY))
        {
                uint32_t tmp_cpsr;
 
@@ -2132,7 +2132,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
                /* read a program status register
                 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
                 */
-               arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
+               arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
        }
 
        if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -2144,9 +2144,9 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
        r->dirty = 0;
        buf_set_u32(r->value, 0, 32, value);
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))    {
+                       && (areg->mode != ARM_MODE_ANY))        {
                /* restore processor mode (mask T bit) */
                arm7_9->write_xpsr_im8(target,
                                buf_get_u32(armv4_5->cpsr->value, 0, 8)
@@ -2157,7 +2157,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
 }
 
 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
-               int num, enum armv4_5_mode mode, uint32_t value)
+               int num, enum arm_mode mode, uint32_t value)
 {
        uint32_t reg[16];
        struct arm_reg *areg = r->arch_info;
@@ -2169,9 +2169,9 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))    {
+                       && (areg->mode != ARM_MODE_ANY))        {
                uint32_t tmp_cpsr;
 
                /* change processor mode (mask T bit) */
@@ -2193,7 +2193,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
                /* write a program status register
                * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
                */
-               int spsr = (areg->mode != ARMV4_5_MODE_ANY);
+               int spsr = (areg->mode != ARM_MODE_ANY);
 
                /* if we're writing the CPSR, mask the T bit */
                if (!spsr)
@@ -2205,9 +2205,9 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
        r->valid = 1;
        r->dirty = 0;
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))    {
+                       && (areg->mode != ARM_MODE_ANY))        {
                /* restore processor mode (mask T bit) */
                arm7_9->write_xpsr_im8(target,
                                buf_get_u32(armv4_5->cpsr->value, 0, 8)
@@ -2383,7 +2383,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                return ERROR_TARGET_DATA_ABORT;
        }
 
-       if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+       if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
        {
                LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
@@ -2571,7 +2571,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
                return ERROR_TARGET_DATA_ABORT;
        }
 
-       if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+       if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
        {
                LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
@@ -2696,9 +2696,9 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
        struct armv4_5_algorithm armv4_5_info;
        struct reg_param reg_params[1];
 
-       armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
-       armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+       armv4_5_info.common_magic = ARM_COMMON_MAGIC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
+       armv4_5_info.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
 
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