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Andreas Fritiofson <andreas.fritiofson@gmail.com> UTF8 fixes
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index c4b7c6a16c26ef52c40de8346ee4741254d5b08e..dfe045d5b6580418162e2037f7cce35e8ad6b041 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -58,6 +58,7 @@ int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char
  */
 static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
 {
+       LOG_DEBUG("-");
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
        arm7_9->sw_breakpoints_added = 0;
@@ -93,6 +94,10 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
        {
                LOG_ERROR("BUG: no hardware comparator available");
        }
+       LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", 
+                         breakpoint->unique_id,
+                         breakpoint->address,
+                         breakpoint->set );
 }
 
 /**
@@ -152,6 +157,8 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
                LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
                return ERROR_FAIL;
        }
+       LOG_DEBUG("SW BP using hw wp: %d", 
+                         arm7_9->sw_breakpoints_added );
 
        return jtag_execute_queue();
 }
@@ -220,6 +227,10 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        int retval = ERROR_OK;
 
+       LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
+                         breakpoint->unique_id,
+                         breakpoint->address );
+
        if (target->state != TARGET_HALTED)
        {
                LOG_WARNING("target not halted");
@@ -343,6 +354,10 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
+       LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
+                         breakpoint->unique_id,
+                         breakpoint->address );
+
        if (!breakpoint->set)
        {
                LOG_WARNING("breakpoint not set");
@@ -351,6 +366,9 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 
        if (breakpoint->type == BKPT_HARD)
        {
+               LOG_DEBUG("BPID: %d Releasing hw wp: %d", 
+                                 breakpoint->unique_id,
+                                 breakpoint->set );
                if (breakpoint->set == 1)
                {
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
@@ -526,7 +544,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
-               if ( watchpoint->mask != 0xffffffffu )
+               if (watchpoint->mask != 0xffffffffu)
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
@@ -543,7 +561,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
-               if ( watchpoint->mask != 0xffffffffu )
+               if (watchpoint->mask != 0xffffffffu)
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
@@ -702,7 +720,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
 
        long long then = timeval_ms();
        int timeout;
-       while (!(timeout = ((timeval_ms()-then)>1000)))
+       while (!(timeout = ((timeval_ms()-then) > 1000)))
        {
                /* read debug status register */
                embeddedice_read_reg(dbg_stat);
@@ -862,11 +880,11 @@ int arm7_9_handle_target_request(void *priv)
  * what happens:
  *
  * <table>
- *             <tr><th>State</th><th>Action</th></tr>
- *             <tr><td>TARGET_RUNNING | TARGET_RESET</td><td>Enters debug mode.  If TARGET_RESET, pc may be checked</td></tr>
- *             <tr><td>TARGET_UNKNOWN</td><td>Warning is logged</td></tr>
- *             <tr><td>TARGET_DEBUG_RUNNING</td><td>Enters debug mode</td></tr>
- *             <tr><td>TARGET_HALTED</td><td>Nothing</td></tr>
+ *             <tr><th > State</th><th > Action</th></tr>
+ *             <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode.  If TARGET_RESET, pc may be checked</td></tr>
+ *             <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
+ *             <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
+ *             <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
  * </table>
  *
  * If the target does not end up in the halted state, a warning is produced.  If
@@ -895,8 +913,9 @@ int arm7_9_poll(target_t *target)
 /*             LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
                if (target->state == TARGET_UNKNOWN)
                {
+                       /* Starting OpenOCD with target in debug-halt */
                        target->state = TARGET_RUNNING;
-                       LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
+                       LOG_DEBUG("DBGACK already set during server startup.");
                }
                if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
                {
@@ -974,7 +993,7 @@ int arm7_9_assert_reset(target_t *target)
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        LOG_DEBUG("target->state: %s",
-                 Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+                 target_state_name(target));
 
        enum reset_types jtag_reset_config = jtag_get_reset_config();
        if (!(jtag_reset_config & RESET_HAS_SRST))
@@ -1044,7 +1063,7 @@ int arm7_9_deassert_reset(target_t *target)
 {
        int retval = ERROR_OK;
        LOG_DEBUG("target->state: %s",
-               Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+               target_state_name(target));
 
        /* deassert reset lines */
        jtag_add_reset(0, 0);
@@ -1152,7 +1171,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 
        long long then = timeval_ms();
        int timeout;
-       while (!(timeout = ((timeval_ms()-then)>1000)))
+       while (!(timeout = ((timeval_ms()-then) > 1000)))
        {
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
                        break;
@@ -1257,7 +1276,7 @@ int arm7_9_halt(target_t *target)
        reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        LOG_DEBUG("target->state: %s",
-                 Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+                 target_state_name(target));
 
        if (target->state == TARGET_HALTED)
        {
@@ -1412,18 +1431,10 @@ int arm7_9_debug_entry(target_t *target)
                context[15] -= 3 * 4;
        }
 
-       if ((target->debug_reason == DBG_REASON_BREAKPOINT)
-                       || (target->debug_reason == DBG_REASON_SINGLESTEP)
-                       || (target->debug_reason == DBG_REASON_WATCHPOINT)
-                       || (target->debug_reason == DBG_REASON_WPTANDBKPT)
-                       || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
+       if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
                context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
-       else if (target->debug_reason == DBG_REASON_DBGRQ)
-               context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
        else
-       {
-               LOG_ERROR("unknown debug reason: %i", target->debug_reason);
-       }
+               context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
@@ -1807,7 +1818,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
        {
                if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
                {
-                       LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
+                       LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
                        if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
                        {
                                return retval;
@@ -1951,7 +1962,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
@@ -2582,7 +2593,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
        int little = target->endianness == TARGET_LITTLE_ENDIAN;
        int count = dcc_count;
        uint8_t *buffer = dcc_buffer;
-       if (count>2)
+       if (count > 2)
        {
                /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
                 * core function repeated. */
@@ -2672,14 +2683,14 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count,
        dcc_count = count;
        dcc_buffer = buffer;
        retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
-                       arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
+                       arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
 
        if (retval == ERROR_OK)
        {
                uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
-               if (endaddress != (address+count*4))
+               if (endaddress != (address + count*4))
                {
-                       LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress);
+                       LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
                        retval = ERROR_FAIL;
                }
        }
@@ -2842,17 +2853,17 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx)
 
        arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
 
-       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
-       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
+       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr | spsr>");
+       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr | spsr>");
 
        register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
 
        register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
-               COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
+               COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable | disable>");
        register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
-                COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses <enable|disable>");
+                COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses <enable | disable>");
        register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
-               COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
+               COMMAND_ANY, "use DCC downloads for larger memory writes <enable | disable>");
 
        armv4_5_register_commands(cmd_ctx);
 
@@ -2884,7 +2895,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
 
        if (argc < 2)
        {
-               command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
+               command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr | spsr>");
                return ERROR_OK;
        }
 
@@ -2929,7 +2940,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
 
        if (argc < 3)
        {
-               command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
+               command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
                return ERROR_OK;
        }
 
@@ -3005,7 +3016,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch
                }
                else
                {
-                       command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
+                       command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable | disable>");
                }
        }
 
@@ -3038,7 +3049,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx,
                }
                else
                {
-                       command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
+                       command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable | disable>");
                }
        }
 
@@ -3071,7 +3082,7 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
                }
                else
                {
-                       command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
+                       command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable | disable>");
                }
        }
 
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|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)