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simplify debug_reason check
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index f6f277102fb63d0e8fc139a38940c10fd506563c..e35940bc9fd0b6b445ca6d4189fb391b9eb48033 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007,2008 �yvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -58,6 +58,7 @@ int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char
  */
 static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
 {
+       LOG_DEBUG("-");
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
        arm7_9->sw_breakpoints_added = 0;
@@ -93,6 +94,10 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
        {
                LOG_ERROR("BUG: no hardware comparator available");
        }
+       LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", 
+                         breakpoint->unique_id,
+                         breakpoint->address,
+                         breakpoint->set );
 }
 
 /**
@@ -118,11 +123,11 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
        /* pick a breakpoint unit */
        if (!arm7_9->wp0_used)
        {
-               arm7_9->sw_breakpoints_added=1;
+               arm7_9->sw_breakpoints_added = 1;
                arm7_9->wp0_used = 3;
        } else if (!arm7_9->wp1_used)
        {
-               arm7_9->sw_breakpoints_added=2;
+               arm7_9->sw_breakpoints_added = 2;
                arm7_9->wp1_used = 3;
        }
        else
@@ -131,7 +136,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
                return ERROR_FAIL;
        }
 
-       if (arm7_9->sw_breakpoints_added==1)
+       if (arm7_9->sw_breakpoints_added == 1)
        {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
@@ -139,7 +144,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
        }
-       else if (arm7_9->sw_breakpoints_added==2)
+       else if (arm7_9->sw_breakpoints_added == 2)
        {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
@@ -152,6 +157,8 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
                LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
                return ERROR_FAIL;
        }
+       LOG_DEBUG("SW BP using hw wp: %d", 
+                         arm7_9->sw_breakpoints_added );
 
        return jtag_execute_queue();
 }
@@ -218,7 +225,11 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-       int retval=ERROR_OK;
+       int retval = ERROR_OK;
+
+       LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
+                         breakpoint->unique_id,
+                         breakpoint->address );
 
        if (target->state != TARGET_HALTED)
        {
@@ -229,15 +240,15 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        if (breakpoint->type == BKPT_HARD)
        {
                /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
-               u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
+               uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 
                /* reassign a hw breakpoint */
-               if (breakpoint->set==0)
+               if (breakpoint->set == 0)
                {
                        arm7_9_assign_wp(arm7_9, breakpoint);
                }
 
-               if (breakpoint->set==1)
+               if (breakpoint->set == 1)
                {
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
@@ -245,7 +256,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
                }
-               else if (breakpoint->set==2)
+               else if (breakpoint->set == 2)
                {
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
@@ -259,11 +270,11 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        return ERROR_OK;
                }
 
-               retval=jtag_execute_queue();
+               retval = jtag_execute_queue();
        }
        else if (breakpoint->type == BKPT_SOFT)
        {
-               if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
+               if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
                        return retval;
 
                /* did we already set this breakpoint? */
@@ -272,7 +283,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 
                if (breakpoint->length == 4)
                {
-                       u32 verify = 0xffffffff;
+                       uint32_t verify = 0xffffffff;
                        /* keep the original instruction in target endianness */
                        if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
                        {
@@ -290,13 +301,13 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        }
                        if (verify != arm7_9->arm_bkpt)
                        {
-                               LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+                               LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
                }
                else
                {
-                       u16 verify = 0xffff;
+                       uint16_t verify = 0xffff;
                        /* keep the original instruction in target endianness */
                        if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
                        {
@@ -314,7 +325,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        }
                        if (verify != arm7_9->thumb_bkpt)
                        {
-                               LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+                               LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
                }
@@ -343,6 +354,10 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
+       LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
+                         breakpoint->unique_id,
+                         breakpoint->address );
+
        if (!breakpoint->set)
        {
                LOG_WARNING("breakpoint not set");
@@ -351,6 +366,9 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 
        if (breakpoint->type == BKPT_HARD)
        {
+               LOG_DEBUG("BPID: %d Releasing hw wp: %d", 
+                                 breakpoint->unique_id,
+                                 breakpoint->set );
                if (breakpoint->set == 1)
                {
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
@@ -371,13 +389,13 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                /* restore original instruction (kept in target endianness) */
                if (breakpoint->length == 4)
                {
-                       u32 current_instr;
+                       uint32_t current_instr;
                        /* check that user program as not modified breakpoint instruction */
-                       if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr)) != ERROR_OK)
+                       if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
                        {
                                return retval;
                        }
-                       if (current_instr==arm7_9->arm_bkpt)
+                       if (current_instr == arm7_9->arm_bkpt)
                                if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
                                {
                                        return retval;
@@ -385,13 +403,13 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                }
                else
                {
-                       u16 current_instr;
+                       uint16_t current_instr;
                        /* check that user program as not modified breakpoint instruction */
-                       if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr)) != ERROR_OK)
+                       if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
                        {
                                return retval;
                        }
-                       if (current_instr==arm7_9->thumb_bkpt)
+                       if (current_instr == arm7_9->thumb_bkpt)
                                if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
                                {
                                        return retval;
@@ -423,7 +441,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       if (arm7_9->breakpoint_count==0)
+       if (arm7_9->breakpoint_count == 0)
        {
                /* make sure we don't have any dangling breakpoints. This is vital upon
                 * GDB connect/disconnect
@@ -469,7 +487,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-       if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+       if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
        {
                return retval;
        }
@@ -478,10 +496,10 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                arm7_9->wp_available++;
 
        arm7_9->breakpoint_count--;
-       if (arm7_9->breakpoint_count==0)
+       if (arm7_9->breakpoint_count == 0)
        {
                /* make sure we don't have any dangling breakpoints */
-               if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
+               if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
                {
                        return retval;
                }
@@ -506,7 +524,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        int rw_mask = 1;
-       u32 mask;
+       uint32_t mask;
 
        mask = watchpoint->length - 1;
 
@@ -526,12 +544,12 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
-               if( watchpoint->mask != 0xffffffffu )
+               if (watchpoint->mask != 0xffffffffu)
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -543,12 +561,12 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
-               if( watchpoint->mask != 0xffffffffu )
+               if (watchpoint->mask != 0xffffffffu)
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -593,7 +611,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
        if (watchpoint->set == 1)
        {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -602,7 +620,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
        else if (watchpoint->set == 2)
        {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -663,7 +681,7 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 
        if (watchpoint->set)
        {
-               if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
+               if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
                {
                        return retval;
                }
@@ -693,16 +711,16 @@ int arm7_9_execute_sys_speed(struct target_s *target)
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        /* set RESTART instruction */
-       jtag_add_end_state(TAP_IDLE);
+       jtag_set_end_state(TAP_IDLE);
        if (arm7_9->need_bypass_before_restart) {
                arm7_9->need_bypass_before_restart = 0;
                arm_jtag_set_instr(jtag_info, 0xf, NULL);
        }
        arm_jtag_set_instr(jtag_info, 0x4, NULL);
 
-       long long then=timeval_ms();
+       long long then = timeval_ms();
        int timeout;
-       while (!(timeout=((timeval_ms()-then)>1000)))
+       while (!(timeout = ((timeval_ms()-then) > 1000)))
        {
                /* read debug status register */
                embeddedice_read_reg(dbg_stat);
@@ -711,7 +729,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
                if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
                                   && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
                        break;
-               if (debug_level>=3)
+               if (debug_level >= 3)
                {
                        alive_sleep(100);
                } else
@@ -721,7 +739,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
        }
        if (timeout)
        {
-               LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
+               LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
                return ERROR_TARGET_TIMEOUT;
        }
 
@@ -738,8 +756,8 @@ int arm7_9_execute_sys_speed(struct target_s *target)
  */
 int arm7_9_execute_fast_sys_speed(struct target_s *target)
 {
-       static int set=0;
-       static u8 check_value[4], check_mask[4];
+       static int set = 0;
+       static uint8_t check_value[4], check_mask[4];
 
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -747,7 +765,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        /* set RESTART instruction */
-       jtag_add_end_state(TAP_IDLE);
+       jtag_set_end_state(TAP_IDLE);
        if (arm7_9->need_bypass_before_restart) {
                arm7_9->need_bypass_before_restart = 0;
                arm_jtag_set_instr(jtag_info, 0xf, NULL);
@@ -764,7 +782,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
                 * */
                buf_set_u32(check_value, 0, 32, 0x9);
                buf_set_u32(check_mask, 0, 32, 0x9);
-               set=1;
+               set = 1;
        }
 
        /* read debug status register */
@@ -781,16 +799,16 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
  * @param buffer Pointer to the buffer that will hold the data
  * @return The result of receiving data from the Embedded ICE unit
  */
-int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
+int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-       u32 *data;
+       uint32_t *data;
        int retval = ERROR_OK;
-       u32 i;
+       uint32_t i;
 
-       data = malloc(size * (sizeof(u32)));
+       data = malloc(size * (sizeof(uint32_t)));
 
        retval = embeddedice_receive(jtag_info, data, size);
 
@@ -840,7 +858,7 @@ int arm7_9_handle_target_request(void *priv)
                /* check W bit */
                if (buf_get_u32(dcc_control->value, 1, 1) == 1)
                {
-                       u32 request;
+                       uint32_t request;
 
                        if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
                        {
@@ -862,11 +880,11 @@ int arm7_9_handle_target_request(void *priv)
  * what happens:
  *
  * <table>
- *             <tr><th>State</th><th>Action</th></tr>
- *             <tr><td>TARGET_RUNNING | TARGET_RESET</td><td>Enters debug mode.  If TARGET_RESET, pc may be checked</td></tr>
- *             <tr><td>TARGET_UNKNOWN</td><td>Warning is logged</td></tr>
- *             <tr><td>TARGET_DEBUG_RUNNING</td><td>Enters debug mode</td></tr>
- *             <tr><td>TARGET_HALTED</td><td>Nothing</td></tr>
+ *             <tr><th > State</th><th > Action</th></tr>
+ *             <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode.  If TARGET_RESET, pc may be checked</td></tr>
+ *             <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
+ *             <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
+ *             <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
  * </table>
  *
  * If the target does not end up in the halted state, a warning is produced.  If
@@ -895,17 +913,19 @@ int arm7_9_poll(target_t *target)
 /*             LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
                if (target->state == TARGET_UNKNOWN)
                {
+                       /* Starting OpenOCD with target in debug-halt */
                        target->state = TARGET_RUNNING;
-                       LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
+                       LOG_DEBUG("DBGACK already set during server startup.");
                }
                if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
                {
-                       int check_pc=0;
+                       int check_pc = 0;
                        if (target->state == TARGET_RESET)
                        {
                                if (target->reset_halt)
                                {
-                                       if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
+                                       enum reset_types jtag_reset_config = jtag_get_reset_config();
+                                       if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
                                        {
                                                check_pc = 1;
                                        }
@@ -920,8 +940,8 @@ int arm7_9_poll(target_t *target)
                        if (check_pc)
                        {
                                reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
-                               u32 t=*((u32 *)reg->value);
-                               if (t!=0)
+                               uint32_t t=*((uint32_t *)reg->value);
+                               if (t != 0)
                                {
                                        LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
                                }
@@ -973,8 +993,9 @@ int arm7_9_assert_reset(target_t *target)
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        LOG_DEBUG("target->state: %s",
-                 Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+                 target_state_name(target));
 
+       enum reset_types jtag_reset_config = jtag_get_reset_config();
        if (!(jtag_reset_config & RESET_HAS_SRST))
        {
                LOG_ERROR("Can't assert SRST");
@@ -1020,7 +1041,7 @@ int arm7_9_assert_reset(target_t *target)
 
        armv4_5_invalidate_core_regs(target);
 
-       if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
+       if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
        {
                /* debug entry was already prepared in arm7_9_assert_reset() */
                target->debug_reason = DBG_REASON_DBGRQ;
@@ -1040,26 +1061,27 @@ int arm7_9_assert_reset(target_t *target)
  */
 int arm7_9_deassert_reset(target_t *target)
 {
-       int retval=ERROR_OK;
+       int retval = ERROR_OK;
        LOG_DEBUG("target->state: %s",
-               Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+               target_state_name(target));
 
        /* deassert reset lines */
        jtag_add_reset(0, 0);
 
-       if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
+       enum reset_types jtag_reset_config = jtag_get_reset_config();
+       if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
        {
                LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
                /* set up embedded ice registers again */
-               if ((retval=target->type->examine(target))!=ERROR_OK)
+               if ((retval = target_examine_one(target)) != ERROR_OK)
                        return retval;
 
-               if ((retval=target_poll(target))!=ERROR_OK)
+               if ((retval = target_poll(target)) != ERROR_OK)
                {
                        return retval;
                }
 
-               if ((retval=target_halt(target))!=ERROR_OK)
+               if ((retval = target_halt(target)) != ERROR_OK)
                {
                        return retval;
                }
@@ -1144,19 +1166,19 @@ int arm7_9_soft_reset_halt(struct target_s *target)
        int i;
        int retval;
 
-       if ((retval=target_halt(target))!=ERROR_OK)
+       if ((retval = target_halt(target)) != ERROR_OK)
                return retval;
 
-       long long then=timeval_ms();
+       long long then = timeval_ms();
        int timeout;
-       while (!(timeout=((timeval_ms()-then)>1000)))
+       while (!(timeout = ((timeval_ms()-then) > 1000)))
        {
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
                        break;
                embeddedice_read_reg(dbg_stat);
-               if ((retval=jtag_execute_queue())!=ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                        return retval;
-               if (debug_level>=3)
+               if (debug_level >= 3)
                {
                        alive_sleep(100);
                } else
@@ -1187,7 +1209,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
        /* if the target is in Thumb state, change to ARM state */
        if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
        {
-               u32 r0_thumb, pc_thumb;
+               uint32_t r0_thumb, pc_thumb;
                LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
                /* Entered debug from Thumb mode */
                armv4_5->core_state = ARMV4_5_STATE_THUMB;
@@ -1243,7 +1265,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
  */
 int arm7_9_halt(target_t *target)
 {
-       if (target->state==TARGET_RESET)
+       if (target->state == TARGET_RESET)
        {
                LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
                return ERROR_OK;
@@ -1254,7 +1276,7 @@ int arm7_9_halt(target_t *target)
        reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        LOG_DEBUG("target->state: %s",
-                 Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+                 target_state_name(target));
 
        if (target->state == TARGET_HALTED)
        {
@@ -1307,10 +1329,10 @@ int arm7_9_halt(target_t *target)
 int arm7_9_debug_entry(target_t *target)
 {
        int i;
-       u32 context[16];
-       u32* context_p[16];
-       u32 r0_thumb, pc_thumb;
-       u32 cpsr;
+       uint32_t context[16];
+       uint32_t* context_p[16];
+       uint32_t r0_thumb, pc_thumb;
+       uint32_t cpsr;
        int retval;
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -1360,7 +1382,7 @@ int arm7_9_debug_entry(target_t *target)
                /* Entered debug from Thumb mode */
                armv4_5->core_state = ARMV4_5_STATE_THUMB;
                arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
-               LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
+               LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 ", pc_thumb: 0x%8.8" PRIx32 "", r0_thumb, pc_thumb);
        }
        else
        {
@@ -1409,31 +1431,23 @@ int arm7_9_debug_entry(target_t *target)
                context[15] -= 3 * 4;
        }
 
-       if ((target->debug_reason == DBG_REASON_BREAKPOINT)
-                       || (target->debug_reason == DBG_REASON_SINGLESTEP)
-                       || (target->debug_reason == DBG_REASON_WATCHPOINT)
-                       || (target->debug_reason == DBG_REASON_WPTANDBKPT)
-                       || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
+       if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
                context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
-       else if (target->debug_reason == DBG_REASON_DBGRQ)
-               context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
        else
-       {
-               LOG_ERROR("unknown debug reason: %i", target->debug_reason);
-       }
+               context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       for (i=0; i<=15; i++)
+       for (i = 0; i <= 15; i++)
        {
-               LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
+               LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
                buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
        }
 
-       LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
+       LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
 
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
@@ -1441,7 +1455,7 @@ int arm7_9_debug_entry(target_t *target)
        /* exceptions other than USR & SYS have a saved program status register */
        if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
        {
-               u32 spsr;
+               uint32_t spsr;
                arm7_9->read_xpsr(target, &spsr, 1);
                if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
@@ -1497,8 +1511,8 @@ int arm7_9_full_context(target_t *target)
         */
        for (i = 0; i < 6; i++)
        {
-               u32 mask = 0;
-               u32* reg_p[16];
+               uint32_t mask = 0;
+               uint32_t* reg_p[16];
                int j;
                int valid = 1;
 
@@ -1512,7 +1526,7 @@ int arm7_9_full_context(target_t *target)
 
                if (!valid)
                {
-                       u32 tmp_cpsr;
+                       uint32_t tmp_cpsr;
 
                        /* change processor mode (and mask T bit) */
                        tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
@@ -1524,7 +1538,7 @@ int arm7_9_full_context(target_t *target)
                        {
                                if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
                                {
-                                       reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
+                                       reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
                                        mask |= 1 << j;
                                        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
                                        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
@@ -1538,7 +1552,7 @@ int arm7_9_full_context(target_t *target)
                        /* check if the PSR has to be read */
                        if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
                        {
-                               arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
+                               arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
                                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
                                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
                        }
@@ -1630,13 +1644,13 @@ int arm7_9_restore_context(target_t *target)
 
                if (dirty)
                {
-                       u32 mask = 0x0;
+                       uint32_t mask = 0x0;
                        int num_regs = 0;
-                       u32 regs[16];
+                       uint32_t regs[16];
 
                        if (mode_change)
                        {
-                               u32 tmp_cpsr;
+                               uint32_t tmp_cpsr;
 
                                /* change processor mode (mask T bit) */
                                tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
@@ -1659,7 +1673,7 @@ int arm7_9_restore_context(target_t *target)
                                        num_regs++;
                                        reg->dirty = 0;
                                        reg->valid = 1;
-                                       LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
+                                       LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32 "", j, armv4_5_mode_strings[i], regs[j]);
                                }
                        }
 
@@ -1672,7 +1686,7 @@ int arm7_9_restore_context(target_t *target)
                        reg_arch_info = reg->arch_info;
                        if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
                        {
-                               LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
+                               LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
                                arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
                        }
                }
@@ -1681,25 +1695,25 @@ int arm7_9_restore_context(target_t *target)
        if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
        {
                /* restore processor mode (mask T bit) */
-               u32 tmp_cpsr;
+               uint32_t tmp_cpsr;
 
                tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
                tmp_cpsr |= armv4_5_number_to_mode(i);
                tmp_cpsr &= ~0x20;
-               LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
+               LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
                arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
        }
        else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
        {
                /* CPSR has been changed, full restore necessary (mask T bit) */
-               LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+               LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
                arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
                armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
                armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
        }
 
        /* restore PC */
-       LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+       LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
        arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
        armv4_5->core_cache->reg_list[15].dirty = 0;
 
@@ -1724,14 +1738,14 @@ int arm7_9_restart_core(struct target_s *target)
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 
        /* set RESTART instruction */
-       jtag_add_end_state(TAP_IDLE);
+       jtag_set_end_state(TAP_IDLE);
        if (arm7_9->need_bypass_before_restart) {
                arm7_9->need_bypass_before_restart = 0;
                arm_jtag_set_instr(jtag_info, 0xf, NULL);
        }
        arm_jtag_set_instr(jtag_info, 0x4, NULL);
 
-       jtag_add_runtest(1, TAP_IDLE);
+       jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE));
        return jtag_execute_queue();
 }
 
@@ -1771,7 +1785,7 @@ void arm7_9_enable_breakpoints(struct target_s *target)
        }
 }
 
-int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
+int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -1796,7 +1810,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
        if (!current)
                buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
 
-       u32 current_pc;
+       uint32_t current_pc;
        current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
 
        /* the front-end may request us not to handle breakpoints */
@@ -1804,19 +1818,19 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
        {
                if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
                {
-                       LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
+                       LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
                        if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
                        {
                                return retval;
                        }
 
                        /* calculate PC of next instruction */
-                       u32 next_pc;
+                       uint32_t next_pc;
                        if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
                        {
-                               u32 current_opcode;
+                               uint32_t current_opcode;
                                target_read_u32(target, current_pc, &current_opcode);
-                               LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
+                               LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
                                return retval;
                        }
 
@@ -1860,9 +1874,9 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
                        }
 
                        arm7_9_debug_entry(target);
-                       LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+                       LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 
-                       LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
+                       LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
                        if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
                        {
                                return retval;
@@ -1931,15 +1945,15 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
        return ERROR_OK;
 }
 
-void arm7_9_enable_eice_step(target_t *target, u32 next_pc)
+void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-       u32 current_pc;
+       uint32_t current_pc;
        current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
 
-       if(next_pc != current_pc)
+       if (next_pc != current_pc)
        {
                /* setup an inverse breakpoint on the current PC
                * - comparator 1 matches the current address
@@ -1948,7 +1962,7 @@ void arm7_9_enable_eice_step(target_t *target, u32 next_pc)
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
@@ -1985,7 +1999,7 @@ void arm7_9_disable_eice_step(target_t *target)
        embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
 }
 
-int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
+int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2002,7 +2016,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
        if (!current)
                buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
 
-       u32 current_pc;
+       uint32_t current_pc;
        current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
 
        /* the front-end may request us not to handle breakpoints */
@@ -2016,12 +2030,12 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
        target->debug_reason = DBG_REASON_SINGLESTEP;
 
        /* calculate PC of next instruction */
-       u32 next_pc;
+       uint32_t next_pc;
        if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
        {
-               u32 current_opcode;
+               uint32_t current_opcode;
                target_read_u32(target, current_pc, &current_opcode);
-               LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
+               LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
                return retval;
        }
 
@@ -2080,8 +2094,8 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 
 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
 {
-       u32* reg_p[16];
-       u32 value;
+       uint32_t* reg_p[16];
+       uint32_t value;
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -2098,7 +2112,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
                        && (mode != armv4_5->core_mode)
                        && (reg_mode != ARMV4_5_MODE_ANY))
        {
-               u32 tmp_cpsr;
+               uint32_t tmp_cpsr;
 
                /* change processor mode (mask T bit) */
                tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
@@ -2144,9 +2158,9 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
        return ERROR_OK;
 }
 
-int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
+int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value)
 {
-       u32 reg[16];
+       uint32_t reg[16];
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
@@ -2161,7 +2175,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
        if ((mode != ARMV4_5_MODE_ANY)
                        && (mode != armv4_5->core_mode)
                        && (reg_mode != ARMV4_5_MODE_ANY))      {
-               u32 tmp_cpsr;
+               uint32_t tmp_cpsr;
 
                /* change processor mode (mask T bit) */
                tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
@@ -2205,20 +2219,20 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
        return jtag_execute_queue();
 }
 
-int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-       u32 reg[16];
-       u32 num_accesses = 0;
+       uint32_t reg[16];
+       uint32_t num_accesses = 0;
        int thisrun_accesses;
        int i;
-       u32 cpsr;
+       uint32_t cpsr;
        int retval;
        int last_reg = 0;
 
-       LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
+       LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
 
        if (target->state != TARGET_HALTED)
        {
@@ -2237,14 +2251,14 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
        reg[0] = address;
        arm7_9->write_core_regs(target, 0x1, reg);
 
-       int j=0;
+       int j = 0;
 
        switch (size)
        {
                case 4:
                        while (num_accesses < count)
                        {
-                               u32 reg_list;
+                               uint32_t reg_list;
                                thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
@@ -2269,7 +2283,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
                                buffer += thisrun_accesses * 4;
                                num_accesses += thisrun_accesses;
 
-                               if ((j++%1024)==0)
+                               if ((j++%1024) == 0)
                                {
                                        keep_alive();
                                }
@@ -2278,7 +2292,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
                case 2:
                        while (num_accesses < count)
                        {
-                               u32 reg_list;
+                               uint32_t reg_list;
                                thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
@@ -2294,7 +2308,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2307,7 +2321,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
                                buffer += thisrun_accesses * 2;
                                num_accesses += thisrun_accesses;
 
-                               if ((j++%1024)==0)
+                               if ((j++%1024) == 0)
                                {
                                        keep_alive();
                                }
@@ -2316,7 +2330,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
                case 1:
                        while (num_accesses < count)
                        {
-                               u32 reg_list;
+                               uint32_t reg_list;
                                thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
@@ -2332,7 +2346,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2344,7 +2358,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
                                buffer += thisrun_accesses * 1;
                                num_accesses += thisrun_accesses;
 
-                               if ((j++%1024)==0)
+                               if ((j++%1024) == 0)
                                {
                                        keep_alive();
                                }
@@ -2359,7 +2373,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       for (i=0; i<=last_reg; i++)
+       for (i = 0; i <= last_reg; i++)
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
 
        arm7_9->read_xpsr(target, &cpsr, 0);
@@ -2371,7 +2385,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 
        if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
        {
-               LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
+               LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
                arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 
@@ -2381,17 +2395,17 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
        return ERROR_OK;
 }
 
-int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
-       u32 reg[16];
-       u32 num_accesses = 0;
+       uint32_t reg[16];
+       uint32_t num_accesses = 0;
        int thisrun_accesses;
        int i;
-       u32 cpsr;
+       uint32_t cpsr;
        int retval;
        int last_reg = 0;
 
@@ -2425,7 +2439,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
                case 4:
                        while (num_accesses < count)
                        {
-                               u32 reg_list;
+                               uint32_t reg_list;
                                thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
@@ -2448,7 +2462,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
                                        retval = arm7_9_execute_fast_sys_speed(target);
                                else
                                        retval = arm7_9_execute_sys_speed(target);
-                               if(retval != ERROR_OK)
+                               if (retval != ERROR_OK)
                                {
                                        return retval;
                                }
@@ -2459,7 +2473,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
                case 2:
                        while (num_accesses < count)
                        {
-                               u32 reg_list;
+                               uint32_t reg_list;
                                thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
@@ -2484,7 +2498,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2496,7 +2510,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
                case 1:
                        while (num_accesses < count)
                        {
-                               u32 reg_list;
+                               uint32_t reg_list;
                                thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
@@ -2519,7 +2533,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2542,7 +2556,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       for (i=0; i<=last_reg; i++)
+       for (i = 0; i <= last_reg; i++)
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
 
        arm7_9->read_xpsr(target, &cpsr, 0);
@@ -2554,7 +2568,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 
        if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
        {
-               LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
+               LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
                arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 
@@ -2565,29 +2579,29 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 }
 
 static int dcc_count;
-static u8 *dcc_buffer;
+static uint8_t *dcc_buffer;
 
-static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
+static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
 {
        int retval = ERROR_OK;
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-       if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
+       if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
                return retval;
 
-       int little=target->endianness==TARGET_LITTLE_ENDIAN;
-       int count=dcc_count;
-       u8 *buffer=dcc_buffer;
-       if (count>2)
+       int little = target->endianness == TARGET_LITTLE_ENDIAN;
+       int count = dcc_count;
+       uint8_t *buffer = dcc_buffer;
+       if (count > 2)
        {
                /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
                 * core function repeated. */
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
-               buffer+=4;
+               buffer += 4;
 
                embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
-               u8 reg_addr = ice_reg->addr & 0x1f;
+               uint8_t reg_addr = ice_reg->addr & 0x1f;
                jtag_tap_t *tap;
                tap = ice_reg->jtag_info->tap;
 
@@ -2605,22 +2619,22 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti
                }
        }
 
-       if((retval = target_halt(target))!= ERROR_OK)
+       if ((retval = target_halt(target))!= ERROR_OK)
        {
                return retval;
        }
        return target_wait_state(target, TARGET_HALTED, 500);
 }
 
-static const u32 dcc_code[] =
+static const uint32_t dcc_code[] =
 {
        /* MRC      TST         BNE         MRC         STR         B */
        0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
 };
 
-int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info));
+int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info));
 
-int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
+int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2633,7 +2647,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
        /* regrab previously allocated working_area, or allocate a new one */
        if (!arm7_9->dcc_working_area)
        {
-               u8 dcc_code_buf[6 * 4];
+               uint8_t dcc_code_buf[6 * 4];
 
                /* make sure we have a working area */
                if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
@@ -2666,18 +2680,18 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 
        buf_set_u32(reg_params[0].value, 0, 32, address);
 
-       dcc_count=count;
-       dcc_buffer=buffer;
+       dcc_count = count;
+       dcc_buffer = buffer;
        retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
-                       arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
+                       arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
 
-       if (retval==ERROR_OK)
+       if (retval == ERROR_OK)
        {
-               u32 endaddress=buf_get_u32(reg_params[0].value, 0, 32);
-               if (endaddress!=(address+count*4))
+               uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
+               if (endaddress != (address + count*4))
                {
-                       LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress);
-                       retval=ERROR_FAIL;
+                       LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
+                       retval = ERROR_FAIL;
                }
        }
 
@@ -2686,14 +2700,14 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
        return retval;
 }
 
-int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
+int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
 {
        working_area_t *crc_algorithm;
        armv4_5_algorithm_t armv4_5_info;
        reg_param_t reg_params[2];
        int retval;
 
-       u32 arm7_9_crc_code[] = {
+       uint32_t arm7_9_crc_code[] = {
                0xE1A02000,                             /* mov          r2, r0 */
                0xE3E00000,                             /* mov          r0, #0xffffffff */
                0xE1A03001,                             /* mov          r3, r1 */
@@ -2721,7 +2735,7 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
                0x04C11DB7                              /* CRC32XOR:    .word 0x04C11DB7 */
        };
 
-       u32 i;
+       uint32_t i;
 
        if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
        {
@@ -2729,9 +2743,9 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
        }
 
        /* convert flash writing code into a buffer in target endianness */
-       for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
+       for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++)
        {
-               if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]))!=ERROR_OK)
+               if ((retval = target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK)
                {
                        return retval;
                }
@@ -2767,15 +2781,15 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
        return ERROR_OK;
 }
 
-int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
+int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
 {
        working_area_t *erase_check_algorithm;
        reg_param_t reg_params[3];
        armv4_5_algorithm_t armv4_5_info;
        int retval;
-       u32 i;
+       uint32_t i;
 
-       u32 erase_check_code[] =
+       uint32_t erase_check_code[] =
        {
                                                /* loop: */
                0xe4d03001,             /* ldrb r3, [r0], #1    */
@@ -2793,8 +2807,8 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u
        }
 
        /* convert flash writing code into a buffer in target endianness */
-       for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
-               if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK)
+       for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint32_t)); i++)
+               if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t), erase_check_code[i])) != ERROR_OK)
                {
                        return retval;
                }
@@ -2839,17 +2853,17 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx)
 
        arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
 
-       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
-       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
+       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr | spsr>");
+       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr | spsr>");
 
        register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
 
        register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
-               COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
+               COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable | disable>");
        register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
-                COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses <enable|disable>");
+                COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses <enable | disable>");
        register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
-               COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
+               COMMAND_ANY, "use DCC downloads for larger memory writes <enable | disable>");
 
        armv4_5_register_commands(cmd_ctx);
 
@@ -2860,7 +2874,7 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx)
 
 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
-       u32 value;
+       uint32_t value;
        int spsr;
        int retval;
        target_t *target = get_current_target(cmd_ctx);
@@ -2881,7 +2895,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
 
        if (argc < 2)
        {
-               command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
+               command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr | spsr>");
                return ERROR_OK;
        }
 
@@ -2904,7 +2918,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
 
 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
-       u32 value;
+       uint32_t value;
        int rotate;
        int spsr;
        int retval;
@@ -2926,7 +2940,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
 
        if (argc < 3)
        {
-               command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
+               command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
                return ERROR_OK;
        }
 
@@ -2946,8 +2960,8 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
 
 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
-       u32 value;
-       u32 mode;
+       uint32_t value;
+       uint32_t mode;
        int num;
        target_t *target = get_current_target(cmd_ctx);
        armv4_5_common_t *armv4_5;
@@ -3002,7 +3016,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch
                }
                else
                {
-                       command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
+                       command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable | disable>");
                }
        }
 
@@ -3035,7 +3049,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx,
                }
                else
                {
-                       command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
+                       command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable | disable>");
                }
        }
 
@@ -3068,7 +3082,7 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
                }
                else
                {
-                       command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
+                       command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable | disable>");
                }
        }
 
@@ -3084,7 +3098,7 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 
        arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
 
-       if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
+       if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
        {
                return retval;
        }
@@ -3117,12 +3131,12 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
        armv4_5->write_core_reg = arm7_9_write_core_reg;
        armv4_5->full_context = arm7_9_full_context;
 
-       if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+       if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
        {
                return retval;
        }
 
-       if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
+       if ((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
        {
                return retval;
        }
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