#include "arm920t.h"
#include "time_support.h"
#include "target_type.h"
-
+#include "register.h"
+
+
+/*
+ * For information about the ARM920T, see ARM DDI 0151C especially
+ * Chapter 9 about debug support, which shows how to manipulate each
+ * of the different scan chains:
+ *
+ * 0 ... ARM920 signals, e.g. to rest of SOC (unused here)
+ * 1 ... debugging; watchpoint and breakpoint status, etc; also
+ * MMU and cache access in conjunction with scan chain 15
+ * 2 ... EmbeddedICE
+ * 3 ... external boundary scan (SoC-specific, unused here)
+ * 4 ... access to cache tag RAM
+ * 6 ... ETM9
+ * 15 ... access coprocessor 15, "physical" or "interpreted" modes
+ * "interpreted" works with a few actual MRC/MCR instructions
+ * "physical" provides register-like behaviors.
+ *
+ * The ARM922T is similar, but with smaller caches (8K each, vs 16K).
+ */
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-/* cli handling */
-int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-
-int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-
-/* forward declarations */
-int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
-int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-
#define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
-static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
-static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
-
-
-target_type_t arm920t_target =
-{
- .name = "arm920t",
-
- .poll = arm7_9_poll,
- .arch_state = arm920t_arch_state,
-
- .target_request_data = arm7_9_target_request_data,
-
- .halt = arm7_9_halt,
- .resume = arm7_9_resume,
- .step = arm7_9_step,
-
- .assert_reset = arm7_9_assert_reset,
- .deassert_reset = arm7_9_deassert_reset,
- .soft_reset_halt = arm920t_soft_reset_halt,
-
- .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
-
- .read_memory = arm920t_read_memory,
- .write_memory = arm920t_write_memory,
- .read_phys_memory = arm920t_read_phys_memory,
- .write_phys_memory = arm920t_write_phys_memory,
- .bulk_write_memory = arm7_9_bulk_write_memory,
- .checksum_memory = arm7_9_checksum_memory,
- .blank_check_memory = arm7_9_blank_check_memory,
-
- .run_algorithm = armv4_5_run_algorithm,
-
- .add_breakpoint = arm7_9_add_breakpoint,
- .remove_breakpoint = arm7_9_remove_breakpoint,
- .add_watchpoint = arm7_9_add_watchpoint,
- .remove_watchpoint = arm7_9_remove_watchpoint,
-
- .register_commands = arm920t_register_commands,
- .target_create = arm920t_target_create,
- .init_target = arm920t_init_target,
- .examine = arm9tdmi_examine,
- .mrc = arm920t_mrc,
- .mcr = arm920t_mcr,
-};
-
-int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
+static int arm920t_read_cp15_physical(struct target *target,
+ int reg_addr, uint32_t *value)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
- scan_field_t fields[4];
+ struct arm920t_common *arm920t = target_to_arm920(target);
+ struct arm_jtag *jtag_info;
+ struct scan_field fields[4];
uint8_t access_type_buf = 1;
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 0;
+ jtag_info = &arm920t->arm7_9_common.jtag_info;
+
jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
- #ifdef _DEBUG_INSTRUCTION_EXECUTION_
+#ifdef _DEBUG_INSTRUCTION_EXECUTION_
jtag_execute_queue();
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
#endif
return ERROR_OK;
}
-int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value)
+static int arm920t_write_cp15_physical(struct target *target,
+ int reg_addr, uint32_t value)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
- scan_field_t fields[4];
+ struct arm920t_common *arm920t = target_to_arm920(target);
+ struct arm_jtag *jtag_info;
+ struct scan_field fields[4];
uint8_t access_type_buf = 1;
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 1;
uint8_t value_buf[4];
+ jtag_info = &arm920t->arm7_9_common.jtag_info;
+
buf_set_u32(value_buf, 0, 32, value);
jtag_set_end_state(TAP_IDLE);
return ERROR_OK;
}
-int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode)
+static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
+ uint32_t arm_opcode)
{
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
- scan_field_t fields[4];
+ struct arm920t_common *arm920t = target_to_arm920(target);
+ struct arm_jtag *jtag_info;
+ struct scan_field fields[4];
uint8_t access_type_buf = 0; /* interpreted access */
uint8_t reg_addr_buf = 0x0;
uint8_t nr_w_buf = 0;
uint8_t cp15_opcode_buf[4];
+ jtag_info = &arm920t->arm7_9_common.jtag_info;
+
jtag_set_end_state(TAP_IDLE);
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
- LOG_ERROR("failed executing JTAG queue, exiting");
+ LOG_ERROR("failed executing JTAG queue");
return retval;
}
return ERROR_OK;
}
-int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value)
+static int arm920t_read_cp15_interpreted(struct target *target,
+ uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
uint32_t* regs_p[1];
uint32_t regs[2];
uint32_t cp15c15 = 0x0;
LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
#endif
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
return ERROR_OK;
}
-int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address)
+static
+int arm920t_write_cp15_interpreted(struct target *target,
+ uint32_t cp15_opcode, uint32_t value, uint32_t address)
{
uint32_t cp15c15 = 0x0;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
uint32_t regs[2];
/* load value, address into R0, R1 */
LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
#endif
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
return ERROR_OK;
}
-uint32_t arm920t_get_ttb(target_t *target)
+// EXPORTED to FA256
+uint32_t arm920t_get_ttb(struct target *target)
{
int retval;
uint32_t ttb = 0x0;
return ttb;
}
-void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
+// EXPORTED to FA256
+void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
{
uint32_t cp15_control;
arm920t_write_cp15_physical(target, 0x2, cp15_control);
}
-void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
+// EXPORTED to FA256
+void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
{
uint32_t cp15_control;
arm920t_write_cp15_physical(target, 0x2, cp15_control);
}
-void arm920t_post_debug_entry(target_t *target)
+// EXPORTED to FA256
+void arm920t_post_debug_entry(struct target *target)
{
uint32_t cp15c15;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
- arm920t_common_t *arm920t = arm9tdmi->arch_info;
+ struct arm920t_common *arm920t = target_to_arm920(target);
/* examine cp15 control reg */
arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
}
}
-void arm920t_pre_restore_context(target_t *target)
+// EXPORTED to FA256
+void arm920t_pre_restore_context(struct target *target)
{
uint32_t cp15c15;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
- arm920t_common_t *arm920t = arm9tdmi->arch_info;
+ struct arm920t_common *arm920t = target_to_arm920(target);
/* restore i/d fault status and address register */
arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
}
}
-int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
-{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm920t_common_t *arm920t;
-
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
- {
- return -1;
- }
-
- arm7_9 = armv4_5->arch_info;
- if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
- {
- return -1;
- }
-
- arm9tdmi = arm7_9->arch_info;
- if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
- {
- return -1;
- }
+static const char arm920_not[] = "target is not an ARM920";
- arm920t = arm9tdmi->arch_info;
- if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
- {
- return -1;
+static int arm920t_verify_pointer(struct command_context *cmd_ctx,
+ struct arm920t_common *arm920t)
+{
+ if (arm920t->common_magic != ARM920T_COMMON_MAGIC) {
+ command_print(cmd_ctx, arm920_not);
+ return ERROR_TARGET_INVALID;
}
- *armv4_5_p = armv4_5;
- *arm7_9_p = arm7_9;
- *arm9tdmi_p = arm9tdmi;
- *arm920t_p = arm920t;
-
return ERROR_OK;
}
-int arm920t_arch_state(struct target_s *target)
+/** Logs summary of ARM920 state for a halted target. */
+int arm920t_arch_state(struct target *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
- arm920t_common_t *arm920t = arm9tdmi->arch_info;
-
- char *state[] =
+ static const char *state[] =
{
"disabled", "enabled"
};
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+ struct arm920t_common *arm920t = target_to_arm920(target);
+ struct armv4_5_common_s *armv4_5;
+
+ if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
{
- LOG_ERROR("BUG: called for a non-ARMv4/5 target");
- exit(-1);
+ LOG_ERROR("BUG: %s", arm920_not);
+ return ERROR_TARGET_INVALID;
}
+ armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
+
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
- armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
+ arm_mode_name(armv4_5->core_mode),
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[arm920t->armv4_5_mmu.mmu_enabled],
return ERROR_OK;
}
-int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int arm920_mmu(struct target *target, int *enabled)
+{
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("%s: target not halted", __func__);
+ return ERROR_TARGET_INVALID;
+ }
+
+ *enabled = target_to_arm920(target)->armv4_5_mmu.mmu_enabled;
+ return ERROR_OK;
+}
+
+static int arm920_virt2phys(struct target *target,
+ uint32_t virt, uint32_t *phys)
+{
+ /** @todo Implement this! */
+ LOG_ERROR("%s: not implemented", __func__);
+ return ERROR_FAIL;
+}
+
+/** Reads a buffer, in the specified word size, with current MMU settings. */
+int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
}
-int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int arm920t_read_phys_memory(struct target *target,
+ uint32_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
- arm920t_common_t *arm920t = arm9tdmi->arch_info;
+ struct arm920t_common *arm920t = target_to_arm920(target);
- return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
+ return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu,
+ address, size, count, buffer);
}
-int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int arm920t_write_phys_memory(struct target *target,
+ uint32_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
- arm920t_common_t *arm920t = arm9tdmi->arch_info;
+ struct arm920t_common *arm920t = target_to_arm920(target);
- return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
+ return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu,
+ address, size, count, buffer);
}
-int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+/** Writes a buffer, in the specified word size, with current MMU settings. */
+int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
- arm920t_common_t *arm920t = arm9tdmi->arch_info;
if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
return retval;
- /* This fn is used to write breakpoints, so we need to make sure that the
- * datacache is flushed and the instruction cache is invalidated */
+ /* This fn is used to write breakpoints, so we need to make sure
+ * that the data cache is flushed and the instruction cache is
+ * invalidated
+ */
if (((size == 4) || (size == 2)) && (count == 1))
{
+ struct arm920t_common *arm920t = target_to_arm920(target);
+
if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
return retval;
}
-int arm920t_soft_reset_halt(struct target_s *target)
+// EXPORTED to FA256
+int arm920t_soft_reset_halt(struct target *target)
{
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
- arm920t_common_t *arm920t = arm9tdmi->arch_info;
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct arm920t_common *arm920t = target_to_arm920(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
{
return ERROR_OK;
}
-int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
-{
- arm9tdmi_init_target(cmd_ctx, target);
-
- return ERROR_OK;
-}
-
-int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
+int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
{
- arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
- arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
+ struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
- /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
- */
- arm9tdmi_init_arch_info(target, arm9tdmi, tap);
+ /* initialize arm7/arm9 specific info (including armv4_5) */
+ arm9tdmi_init_arch_info(target, arm7_9, tap);
- arm9tdmi->arch_info = arm920t;
arm920t->common_magic = ARM920T_COMMON_MAGIC;
arm7_9->post_debug_entry = arm920t_post_debug_entry;
return ERROR_OK;
}
-int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm920t_target_create(struct target *target, Jim_Interp *interp)
{
- arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
-
- arm920t_init_arch_info(target, arm920t, target->tap);
+ struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common));
- return ERROR_OK;
+ return arm920t_init_arch_info(target, arm920t, target->tap);
}
-int arm920t_register_commands(struct command_context_s *cmd_ctx)
-{
- int retval;
- command_t *arm920t_cmd;
-
-
- retval = arm9tdmi_register_commands(cmd_ctx);
-
- arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
-
- register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
- register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
- register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
-
- register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
- register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
-
- return retval;
-}
-
-int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(arm920t_handle_read_cache_command)
{
int retval = ERROR_OK;
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm920t_common_t *arm920t;
- arm_jtag_t *jtag_info;
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm920t_common *arm920t = target_to_arm920(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
uint32_t C15_C_D_Ind, C15_C_I_Ind;
int i;
FILE *output;
- arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
+ struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
int segment, index;
- if (argc != 1)
+ retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (CMD_ARGC != 1)
{
- command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
+ command_print(CMD_CTX, "usage: arm920t read_cache <filename>");
return ERROR_OK;
}
- if ((output = fopen(args[0], "w")) == NULL)
+ if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
{
LOG_DEBUG("error opening cache content file");
return ERROR_OK;
for (i = 0; i < 16; i++)
regs_p[i] = ®s[i];
- if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM920t target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
/* disable MMU and Caches */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
if ((retval = jtag_execute_queue()) != ERROR_OK)
/* restore CP15 MMU and Cache settings */
arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
- command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
+ command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]);
fclose(output);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* mark registers dirty. */
return ERROR_OK;
}
-int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(arm920t_handle_read_mmu_command)
{
int retval = ERROR_OK;
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm920t_common_t *arm920t;
- arm_jtag_t *jtag_info;
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm920t_common *arm920t = target_to_arm920(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
int i;
FILE *output;
uint32_t Dlockdown, Ilockdown;
- arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
+ struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
int victim;
- if (argc != 1)
+ retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (CMD_ARGC != 1)
{
- command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
+ command_print(CMD_CTX, "usage: arm920t read_mmu <filename>");
return ERROR_OK;
}
- if ((output = fopen(args[0], "w")) == NULL)
+ if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
{
LOG_DEBUG("error opening mmu content file");
return ERROR_OK;
for (i = 0; i < 16; i++)
regs_p[i] = ®s[i];
- if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM920t target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
/* disable MMU and Caches */
arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
if ((retval = jtag_execute_queue()) != ERROR_OK)
fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
}
- command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
+ command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]);
fclose(output);
- if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+ if (!is_arm_mode(armv4_5->core_mode))
return ERROR_FAIL;
/* mark registers dirty */
return ERROR_OK;
}
-int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+
+COMMAND_HANDLER(arm920t_handle_cp15_command)
{
int retval;
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm920t_common_t *arm920t;
- arm_jtag_t *jtag_info;
-
- if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM920t target");
- return ERROR_OK;
- }
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm920t_common *arm920t = target_to_arm920(target);
- jtag_info = &arm7_9->jtag_info;
+ retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+ if (retval != ERROR_OK)
+ return retval;
if (target->state != TARGET_HALTED)
{
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
+ command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}
/* one or more argument, access a single register (write if second argument is given */
- if (argc >= 1)
+ if (CMD_ARGC >= 1)
{
- int address = strtoul(args[0], NULL, 0);
+ int address;
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address);
- if (argc == 1)
+ if (CMD_ARGC == 1)
{
uint32_t value;
if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
{
- command_print(cmd_ctx, "couldn't access reg %i", address);
+ command_print(CMD_CTX, "couldn't access reg %i", address);
return ERROR_OK;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
}
- command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
+ command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
}
- else if (argc == 2)
+ else if (CMD_ARGC == 2)
{
- uint32_t value = strtoul(args[1], NULL, 0);
+ uint32_t value;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
{
- command_print(cmd_ctx, "couldn't access reg %i", address);
+ command_print(CMD_CTX, "couldn't access reg %i", address);
return ERROR_OK;
}
- command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
+ command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
}
}
return ERROR_OK;
}
-int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(arm920t_handle_cp15i_command)
{
int retval;
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm920t_common_t *arm920t;
- arm_jtag_t *jtag_info;
-
- if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM920t target");
- return ERROR_OK;
- }
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm920t_common *arm920t = target_to_arm920(target);
+
+ retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+ if (retval != ERROR_OK)
+ return retval;
- jtag_info = &arm7_9->jtag_info;
if (target->state != TARGET_HALTED)
{
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
+ command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}
/* one or more argument, access a single register (write if second argument is given */
- if (argc >= 1)
+ if (CMD_ARGC >= 1)
{
- uint32_t opcode = strtoul(args[0], NULL, 0);
+ uint32_t opcode;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
- if (argc == 1)
+ if (CMD_ARGC == 1)
{
uint32_t value;
if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
{
- command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
+ command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
return ERROR_OK;
}
- command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
+ command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
}
- else if (argc == 2)
+ else if (CMD_ARGC == 2)
{
- uint32_t value = strtoul(args[1], NULL, 0);
+ uint32_t value;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
{
- command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
+ command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
return ERROR_OK;
}
- command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
+ command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
}
- else if (argc == 3)
+ else if (CMD_ARGC == 3)
{
- uint32_t value = strtoul(args[1], NULL, 0);
- uint32_t address = strtoul(args[2], NULL, 0);
+ uint32_t value;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
+ uint32_t address;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
{
- command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
+ command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
return ERROR_OK;
}
- command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
+ command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
}
}
else
{
- command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
+ command_print(CMD_CTX, "usage: arm920t cp15i <opcode> [value] [address]");
}
return ERROR_OK;
}
-int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(arm920t_handle_cache_info_command)
{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm920t_common_t *arm920t;
+ int retval;
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm920t_common *arm920t = target_to_arm920(target);
- if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM920t target");
- return ERROR_OK;
- }
+ retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+ if (retval != ERROR_OK)
+ return retval;
- return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
+ return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache);
}
-static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
if (cpnum!=15)
{
return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
}
-static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
if (cpnum!=15)
{
return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
}
+
+/** Registers commands to access coprocessor, cache, and MMU resources. */
+int arm920t_register_commands(struct command_context *cmd_ctx)
+{
+ int retval;
+ struct command *arm920t_cmd;
+
+ retval = arm9tdmi_register_commands(cmd_ctx);
+
+ arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t",
+ NULL, COMMAND_ANY,
+ "arm920t specific commands");
+
+ register_command(cmd_ctx, arm920t_cmd, "cp15",
+ arm920t_handle_cp15_command, COMMAND_EXEC,
+ "display/modify cp15 register <num> [value]");
+ register_command(cmd_ctx, arm920t_cmd, "cp15i",
+ arm920t_handle_cp15i_command, COMMAND_EXEC,
+ "display/modify cp15 (interpreted access) "
+ "<opcode> [value] [address]");
+ register_command(cmd_ctx, arm920t_cmd, "cache_info",
+ arm920t_handle_cache_info_command, COMMAND_EXEC,
+ "display information about target caches");
+ register_command(cmd_ctx, arm920t_cmd, "read_cache",
+ arm920t_handle_read_cache_command, COMMAND_EXEC,
+ "display I/D cache content");
+ register_command(cmd_ctx, arm920t_cmd, "read_mmu",
+ arm920t_handle_read_mmu_command, COMMAND_EXEC,
+ "display I/D mmu content");
+
+ return retval;
+}
+
+/** Holds methods for ARM920 targets. */
+struct target_type arm920t_target =
+{
+ .name = "arm920t",
+
+ .poll = arm7_9_poll,
+ .arch_state = arm920t_arch_state,
+
+ .target_request_data = arm7_9_target_request_data,
+
+ .halt = arm7_9_halt,
+ .resume = arm7_9_resume,
+ .step = arm7_9_step,
+
+ .assert_reset = arm7_9_assert_reset,
+ .deassert_reset = arm7_9_deassert_reset,
+ .soft_reset_halt = arm920t_soft_reset_halt,
+
+ .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+ .read_memory = arm920t_read_memory,
+ .write_memory = arm920t_write_memory,
+ .read_phys_memory = arm920t_read_phys_memory,
+ .write_phys_memory = arm920t_write_phys_memory,
+ .mmu = arm920_mmu,
+ .virt2phys = arm920_virt2phys,
+
+ .bulk_write_memory = arm7_9_bulk_write_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
+
+ .run_algorithm = armv4_5_run_algorithm,
+
+ .add_breakpoint = arm7_9_add_breakpoint,
+ .remove_breakpoint = arm7_9_remove_breakpoint,
+ .add_watchpoint = arm7_9_add_watchpoint,
+ .remove_watchpoint = arm7_9_remove_watchpoint,
+
+ .register_commands = arm920t_register_commands,
+ .target_create = arm920t_target_create,
+ .init_target = arm9tdmi_init_target,
+ .examine = arm7_9_examine,
+ .mrc = arm920t_mrc,
+ .mcr = arm920t_mcr,
+};
Code Review / openocd.git / blobdiff