+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
- retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{
struct arm *arm = target_to_arm(target);
- uint32_t *regs_p[1];
- uint32_t regs[2];
+ uint32_t *regs_p[16];
+ uint32_t regs[16];
uint32_t cp15c15 = 0x0;
struct reg *r = arm->core_cache->reg_list;
return ERROR_FAIL;
}
- r[0].dirty = 1;
- r[1].dirty = 1;
+ r[0].dirty = true;
+ r[1].dirty = true;
return ERROR_OK;
}
{
uint32_t cp15c15 = 0x0;
struct arm *arm = target_to_arm(target);
- uint32_t regs[2];
+ uint32_t regs[16];
struct reg *r = arm->core_cache->reg_list;
/* load value, address into R0, R1 */
return ERROR_FAIL;
}
- r[0].dirty = 1;
- r[1].dirty = 1;
+ r[0].dirty = true;
+ r[1].dirty = true;
return ERROR_OK;
}
/* EXPORTED to FA256 */
void arm920t_pre_restore_context(struct target *target)
{
- uint32_t cp15c15;
+ uint32_t cp15c15 = 0;
struct arm920t_common *arm920t = target_to_arm920(target);
/* restore i/d fault status and address register */
static const char arm920_not[] = "target is not an ARM920";
-static int arm920t_verify_pointer(struct command_context *cmd_ctx,
+static int arm920t_verify_pointer(struct command_invocation *cmd,
struct arm920t_common *arm920t)
{
if (arm920t->common_magic != ARM920T_COMMON_MAGIC) {
- command_print(cmd_ctx, arm920_not);
+ command_print(cmd, arm920_not);
return ERROR_TARGET_INVALID;
}
static int arm920_mmu(struct target *target, int *enabled)
{
if (target->state != TARGET_HALTED) {
- LOG_ERROR("%s: target not halted", __func__);
- return ERROR_TARGET_INVALID;
+ LOG_TARGET_ERROR(target, "not halted");
+ return ERROR_TARGET_NOT_HALTED;
}
*enabled = target_to_arm920(target)->armv4_5_mmu.mmu_enabled;
}
static int arm920_virt2phys(struct target *target,
- uint32_t virt, uint32_t *phys)
+ target_addr_t virt, target_addr_t *phys)
{
uint32_t cb;
struct arm920t_common *arm920t = target_to_arm920(target);
}
/** Reads a buffer, in the specified word size, with current MMU settings. */
-int arm920t_read_memory(struct target *target, uint32_t address,
+int arm920t_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
static int arm920t_read_phys_memory(struct target *target,
- uint32_t address, uint32_t size,
+ target_addr_t address, uint32_t size,
uint32_t count, uint8_t *buffer)
{
struct arm920t_common *arm920t = target_to_arm920(target);
}
static int arm920t_write_phys_memory(struct target *target,
- uint32_t address, uint32_t size,
+ target_addr_t address, uint32_t size,
uint32_t count, const uint8_t *buffer)
{
struct arm920t_common *arm920t = target_to_arm920(target);
}
/** Writes a buffer, in the specified word size, with current MMU settings. */
-int arm920t_write_memory(struct target *target, uint32_t address,
+int arm920t_write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
- int timeout;
+ int64_t then = timeval_ms();
+ bool timeout;
while (!(timeout = ((timeval_ms()-then) > 1000))) {
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
embeddedice_read_reg(dbg_stat);
cpsr &= ~0xff;
cpsr |= 0xd3;
arm_set_cpsr(arm, cpsr);
- arm->cpsr->dirty = 1;
+ arm->cpsr->dirty = true;
/* start fetching from 0x0 */
buf_set_u32(arm->pc->value, 0, 32, 0x0);
- arm->pc->dirty = 1;
- arm->pc->valid = 1;
+ arm->pc->dirty = true;
+ arm->pc->valid = true;
arm920t_disable_mmu_caches(target, 1, 1, 1);
arm920t->armv4_5_mmu.mmu_enabled = 0;
/* FIXME remove forward decls */
static int arm920t_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
+ uint32_t crn, uint32_t crm,
uint32_t *value);
static int arm920t_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
+ uint32_t crn, uint32_t crm,
uint32_t value);
static int arm920t_init_arch_info(struct target *target,
return arm920t_init_arch_info(target, arm920t, target->tap);
}
+static void arm920t_deinit_target(struct target *target)
+{
+ struct arm *arm = target_to_arm(target);
+ struct arm920t_common *arm920t = target_to_arm920(target);
+
+ arm7_9_deinit(target);
+ arm_free_reg_cache(arm);
+ free(arm920t);
+}
+
COMMAND_HANDLER(arm920t_handle_read_cache_command)
{
int retval = ERROR_OK;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t regs[16];
uint32_t *regs_p[16];
- uint32_t C15_C_D_Ind, C15_C_I_Ind;
+ uint32_t c15_c_d_ind, c15_c_i_ind;
int i;
FILE *output;
int segment, index_t;
struct reg *r;
- retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+ retval = arm920t_verify_pointer(CMD, arm920t);
if (retval != ERROR_OK)
return retval;
return ERROR_COMMAND_SYNTAX_ERROR;
output = fopen(CMD_ARGV[0], "w");
- if (output == NULL) {
+ if (!output) {
LOG_DEBUG("error opening cache content file");
return ERROR_OK;
}
/* read current victim */
arm920t_read_cp15_physical(target,
- CP15PHYS_DCACHE_IDX, &C15_C_D_Ind);
+ CP15PHYS_DCACHE_IDX, &c15_c_d_ind);
/* clear interpret mode */
cp15c15 &= ~0x1;
}
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
- regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
+ regs[0] = 0x0 | (segment << 5) | (c15_c_d_ind << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
/* read current victim */
arm920t_read_cp15_physical(target, CP15PHYS_ICACHE_IDX,
- &C15_C_I_Ind);
+ &c15_c_i_ind);
/* clear interpret mode */
cp15c15 &= ~0x1;
}
/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
- regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
+ regs[0] = 0x0 | (segment << 5) | (c15_c_d_ind << 26);
arm9tdmi_write_core_regs(target, 0x1, regs);
/* set interpret mode */
/* restore CP15 MMU and Cache settings */
arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved);
- command_print(CMD_CTX, "cache content successfully output to %s",
+ command_print(CMD, "cache content successfully output to %s",
CMD_ARGV[0]);
fclose(output);
uint32_t *regs_p[16];
int i;
FILE *output;
- uint32_t Dlockdown, Ilockdown;
+ uint32_t d_lockdown, i_lockdown;
struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
int victim;
struct reg *r;
- retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+ retval = arm920t_verify_pointer(CMD, arm920t);
if (retval != ERROR_OK)
return retval;
return ERROR_COMMAND_SYNTAX_ERROR;
output = fopen(CMD_ARGV[0], "w");
- if (output == NULL) {
+ if (!output) {
LOG_DEBUG("error opening mmu content file");
return ERROR_OK;
}
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
- Dlockdown = regs[1];
+ d_lockdown = regs[1];
for (victim = 0; victim < 64; victim += 8) {
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63
*/
- regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
+ regs[1] = (d_lockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
/* set interpret mode */
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63
*/
- regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
+ regs[1] = (d_lockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
/* set interpret mode */
}
/* restore D TLB lockdown */
- regs[1] = Dlockdown;
+ regs[1] = d_lockdown;
arm9tdmi_write_core_regs(target, 0x2, regs);
/* Write D TLB lockdown */
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
- Ilockdown = regs[1];
+ i_lockdown = regs[1];
for (victim = 0; victim < 64; victim += 8) {
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63
*/
- regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
+ regs[1] = (i_lockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
/* set interpret mode */
/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
* base remains unchanged, victim goes through entries 0 to 63
*/
- regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
+ regs[1] = (d_lockdown & 0xfc000000) | (victim << 20);
arm9tdmi_write_core_regs(target, 0x2, regs);
/* set interpret mode */
}
/* restore I TLB lockdown */
- regs[1] = Ilockdown;
+ regs[1] = i_lockdown;
arm9tdmi_write_core_regs(target, 0x2, regs);
/* Write I TLB lockdown */
(i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
}
- command_print(CMD_CTX, "mmu content successfully output to %s",
+ command_print(CMD, "mmu content successfully output to %s",
CMD_ARGV[0]);
fclose(output);
struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target);
- retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+ retval = arm920t_verify_pointer(CMD, arm920t);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
- command_print(CMD_CTX, "target must be stopped for "
+ command_print(CMD, "Error: target must be stopped for "
"\"%s\" command", CMD_NAME);
- return ERROR_OK;
+ return ERROR_TARGET_NOT_HALTED;
}
/* one argument, read a register.
uint32_t value;
retval = arm920t_read_cp15_physical(target, address, &value);
if (retval != ERROR_OK) {
- command_print(CMD_CTX,
+ command_print(CMD,
"couldn't access reg %i", address);
return ERROR_OK;
}
if (retval != ERROR_OK)
return retval;
- command_print(CMD_CTX, "%i: %8.8" PRIx32,
+ command_print(CMD, "%i: %8.8" PRIx32,
address, value);
} else if (CMD_ARGC == 2) {
uint32_t value;
retval = arm920t_write_cp15_physical(target,
address, value);
if (retval != ERROR_OK) {
- command_print(CMD_CTX,
+ command_print(CMD,
"couldn't access reg %i", address);
/* REVISIT why lie? "return retval"? */
return ERROR_OK;
}
- command_print(CMD_CTX, "%i: %8.8" PRIx32,
+ command_print(CMD, "%i: %8.8" PRIx32,
address, value);
}
}
return ERROR_OK;
}
-COMMAND_HANDLER(arm920t_handle_cp15i_command)
-{
- int retval;
- struct target *target = get_current_target(CMD_CTX);
- struct arm920t_common *arm920t = target_to_arm920(target);
-
- retval = arm920t_verify_pointer(CMD_CTX, arm920t);
- if (retval != ERROR_OK)
- return retval;
-
-
- if (target->state != TARGET_HALTED) {
- command_print(CMD_CTX, "target must be stopped for "
- "\"%s\" command", CMD_NAME);
- return ERROR_OK;
- }
-
- /* one argument, read a register.
- * two arguments, write it.
- */
- if (CMD_ARGC >= 1) {
- uint32_t opcode;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
-
- if (CMD_ARGC == 1) {
- uint32_t value;
- retval = arm920t_read_cp15_interpreted(target,
- opcode, 0x0, &value);
- if (retval != ERROR_OK) {
- command_print(CMD_CTX,
- "couldn't execute %8.8" PRIx32,
- opcode);
- /* REVISIT why lie? "return retval"? */
- return ERROR_OK;
- }
-
- command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32,
- opcode, value);
- } else if (CMD_ARGC == 2) {
- uint32_t value;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
- retval = arm920t_write_cp15_interpreted(target,
- opcode, value, 0);
- if (retval != ERROR_OK) {
- command_print(CMD_CTX,
- "couldn't execute %8.8" PRIx32,
- opcode);
- /* REVISIT why lie? "return retval"? */
- return ERROR_OK;
- }
- command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32,
- opcode, value);
- } else if (CMD_ARGC == 3) {
- uint32_t value;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
- uint32_t address;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
- retval = arm920t_write_cp15_interpreted(target,
- opcode, value, address);
- if (retval != ERROR_OK) {
- command_print(CMD_CTX,
- "couldn't execute %8.8" PRIx32, opcode);
- /* REVISIT why lie? "return retval"? */
- return ERROR_OK;
- }
- command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32
- " %8.8" PRIx32, opcode, value, address);
- }
- } else
- return ERROR_COMMAND_SYNTAX_ERROR;
-
- return ERROR_OK;
-}
-
COMMAND_HANDLER(arm920t_handle_cache_info_command)
{
int retval;
struct target *target = get_current_target(CMD_CTX);
struct arm920t_common *arm920t = target_to_arm920(target);
- retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+ retval = arm920t_verify_pointer(CMD, arm920t);
if (retval != ERROR_OK)
return retval;
- return armv4_5_handle_cache_info_command(CMD_CTX,
+ return armv4_5_handle_cache_info_command(CMD,
&arm920t->armv4_5_mmu.armv4_5_cache);
}
static int arm920t_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
+ uint32_t crn, uint32_t crm,
uint32_t *value)
{
if (cpnum != 15) {
/* read "to" r0 */
return arm920t_read_cp15_interpreted(target,
- ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
+ ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
0, value);
}
static int arm920t_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
+ uint32_t crn, uint32_t crm,
uint32_t value)
{
if (cpnum != 15) {
/* write "from" r0 */
return arm920t_write_cp15_interpreted(target,
- ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
+ ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
0, value);
}
.help = "display/modify cp15 register",
.usage = "regnum [value]",
},
- {
- .name = "cp15i",
- .handler = arm920t_handle_cp15i_command,
- .mode = COMMAND_EXEC,
- /* prefer using less error-prone "arm mcr" or "arm mrc" */
- .help = "display/modify cp15 register using ARM opcode"
- " (DEPRECATED)",
- .usage = "instruction [value [address]]",
- },
{
.name = "cache_info",
.handler = arm920t_handle_cache_info_command,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm920t_soft_reset_halt,
+ .get_gdb_arch = arm_get_gdb_arch,
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm920t_read_memory,
.commands = arm920t_command_handlers,
.target_create = arm920t_target_create,
.init_target = arm9tdmi_init_target,
+ .deinit_target = arm920t_deinit_target,
.examine = arm7_9_examine,
.check_reset = arm7_9_check_reset,
};
Code Review / openocd.git / blobdiff