jtag_add_dr_scan(4, fields, jtag_get_end_state());
- /*TODO: add timeout*/
- do
+ long long then = timeval_ms();
+
+ for (;;)
{
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
- jtag_add_callback(arm_le_to_h_u32, (uint8_t *)value);
+ jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
- } while (buf_get_u32(&access, 0, 1) != 1);
+
+ if (buf_get_u32(&access, 0, 1) == 1)
+ {
+ break;
+ }
+
+ /* 10ms timeout */
+ if ((timeval_ms()-then)>10)
+ {
+ LOG_ERROR("cp15 read operation timed out");
+ return ERROR_FAIL;
+ }
+ }
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
- /*TODO: add timeout*/
- do
+
+ long long then = timeval_ms();
+
+ for (;;)
{
/* rescan with NOP, to wait for the access to complete */
access = 0;
{
return retval;
}
- } while (buf_get_u32(&access, 0, 1) != 1);
+
+ if (buf_get_u32(&access, 0, 1) == 1)
+ {
+ break;
+ }
+
+ /* 10ms timeout */
+ if ((timeval_ms()-then)>10)
+ {
+ LOG_ERROR("cp15 write operation timed out");
+ return ERROR_FAIL;
+ }
+ }
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
return ERROR_OK;
}
-int arm926ejs_examine_debug_reason(target_t *target)
+static int arm926ejs_examine_debug_reason(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
+ /* Method-Of-Entry (MOE) field */
debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
switch (debug_reason)
{
+ case 0:
+ LOG_DEBUG("no *NEW* debug entry (?missed one?)");
+ /* ... since last restart or debug reset ... */
+ target->debug_reason = DBG_REASON_DBGRQ;
+ break;
case 1:
LOG_DEBUG("breakpoint from EICE unit 0");
target->debug_reason = DBG_REASON_BREAKPOINT;
target->debug_reason = DBG_REASON_DBGRQ;
break;
case 11:
- LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
+ LOG_DEBUG("debug re-entry from system speed access");
+ /* This is normal when connecting to something that's
+ * already halted, or in some related code paths, but
+ * otherwise is surprising (and presumably wrong).
+ */
+ switch (target->debug_reason) {
+ case DBG_REASON_DBGRQ:
+ break;
+ default:
+ LOG_ERROR("unexpected -- debug re-entry");
+ /* FALLTHROUGH */
+ case DBG_REASON_UNDEFINED:
+ target->debug_reason = DBG_REASON_DBGRQ;
+ break;
+ }
break;
case 12:
/* FIX!!!! here be dragons!!! We need to fail here so
* openocd development mailing list if you have hardware
* to donate to look into this problem....
*/
- LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
+ LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
target->debug_reason = DBG_REASON_DBGRQ;
- retval = ERROR_TARGET_FAILURE;
break;
default:
- LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
+ LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason);
+ /* Oh agony! should we interpret this as a halt request or
+ * that the target stopped on it's own accord?
+ */
target->debug_reason = DBG_REASON_DBGRQ;
/* if we fail here, we won't talk to the target and it will
* be reported to be in the halted state */
- retval = ERROR_TARGET_FAILURE;
break;
}
- return retval;
+ return ERROR_OK;
}
uint32_t arm926ejs_get_ttb(target_t *target)
/* examine cp15 control reg */
arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
jtag_execute_queue();
- LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
+ LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
{
arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
- LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
+ LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
uint32_t cache_dbg_ctrl;
LOG_USER(
"target halted in %s state due to %s, current mode: %s\n"
- "cpsr: 0x%8.8x pc: 0x%8.8x\n"
+ "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
- Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
+ Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
return retval;
}
- long long then=timeval_ms();
+ long long then = timeval_ms();
int timeout;
- while (!(timeout=((timeval_ms()-then)>1000)))
+ while (!(timeout = ((timeval_ms()-then) > 1000)))
{
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
{
{
break;
}
- if (debug_level>=1)
+ if (debug_level >= 1)
{
/* do not eat all CPU, time out after 1 se*/
alive_sleep(100);
return retval;
}
- command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
+ command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
}
else
{
command_print(cmd_ctx, "couldn't access register");
return ERROR_OK;
}
- command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
+ command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
}
return ERROR_OK;
Code Review / openocd.git / blobdiff