Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
Fix "unused variable" warnings (errors) detected with GCC 4.7.0 - trivial fixes
[openocd.git] / src / target / arm926ejs.c
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index d81119667b0ec0d7bb0a9c958a55400a55096c85..873e9a033e73b7029a64b8014b7482a33b19e391 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -59,48 +59,44 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
        struct scan_field fields[4];
        uint8_t address_buf[2] = {0, 0};
        uint8_t nr_w_buf = 0;
-       uint8_t access = 1;
+       uint8_t access_t = 1;
 
        buf_set_u32(address_buf, 0, 14, address);
 
-       jtag_set_end_state(TAP_IDLE);
-       if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+       if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
        {
                return retval;
        }
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
-       fields[0].tap = jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
        fields[0].in_value = (uint8_t *)value;
 
-
-       fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 1;
-       fields[1].out_value = &access;
-       fields[1].in_value = &access;
+       fields[1].out_value = &access_t;
+       fields[1].in_value = &access_t;
 
-       fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 14;
        fields[2].out_value = address_buf;
        fields[2].in_value = NULL;
 
-       fields[3].tap = jtag_info->tap;
        fields[3].num_bits = 1;
        fields[3].out_value = &nr_w_buf;
        fields[3].in_value = NULL;
 
-       jtag_add_dr_scan(4, fields, jtag_get_end_state());
+       jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
        long long then = timeval_ms();
 
        for (;;)
        {
                /* rescan with NOP, to wait for the access to complete */
-               access = 0;
+               access_t = 0;
                nr_w_buf = 0;
-               jtag_add_dr_scan(4, fields, jtag_get_end_state());
+               jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
                jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
 
@@ -109,7 +105,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
                        return retval;
                }
 
-               if (buf_get_u32(&access, 0, 1) == 1)
+               if (buf_get_u32(&access_t, 0, 1) == 1)
                {
                        break;
                }
@@ -126,7 +122,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
        LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 #endif
 
-       arm_jtag_set_instr(jtag_info, 0xc, NULL);
+       retval = arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        return ERROR_OK;
 }
@@ -152,54 +150,51 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
        uint8_t value_buf[4];
        uint8_t address_buf[2] = {0, 0};
        uint8_t nr_w_buf = 1;
-       uint8_t access = 1;
+       uint8_t access_t = 1;
 
        buf_set_u32(address_buf, 0, 14, address);
        buf_set_u32(value_buf, 0, 32, value);
 
-       jtag_set_end_state(TAP_IDLE);
-       if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+       if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
        {
                return retval;
        }
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
-       fields[0].tap = jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = value_buf;
        fields[0].in_value = NULL;
 
-       fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 1;
-       fields[1].out_value = &access;
-       fields[1].in_value = &access;
+       fields[1].out_value = &access_t;
+       fields[1].in_value = &access_t;
 
-       fields[2].tap = jtag_info->tap;
        fields[2].num_bits = 14;
        fields[2].out_value = address_buf;
        fields[2].in_value = NULL;
 
-       fields[3].tap = jtag_info->tap;
        fields[3].num_bits = 1;
        fields[3].out_value = &nr_w_buf;
        fields[3].in_value = NULL;
 
-       jtag_add_dr_scan(4, fields, jtag_get_end_state());
+       jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
        long long then = timeval_ms();
 
        for (;;)
        {
                /* rescan with NOP, to wait for the access to complete */
-               access = 0;
+               access_t = 0;
                nr_w_buf = 0;
-               jtag_add_dr_scan(4, fields, jtag_get_end_state());
+               jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
                if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
 
-               if (buf_get_u32(&access, 0, 1) == 1)
+               if (buf_get_u32(&access_t, 0, 1) == 1)
                {
                        break;
                }
@@ -216,7 +211,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
        LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 #endif
 
-       arm_jtag_set_instr(jtag_info, 0xf, NULL);
+       retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        return ERROR_OK;
 }
@@ -334,7 +331,7 @@ static int arm926ejs_examine_debug_reason(struct target *target)
        return ERROR_OK;
 }
 
-static uint32_t arm926ejs_get_ttb(struct target *target)
+static int arm926ejs_get_ttb(struct target *target, uint32_t *result)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
        int retval;
@@ -343,23 +340,32 @@ static uint32_t arm926ejs_get_ttb(struct target *target)
        if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
                return retval;
 
-       return ttb;
+       *result = ttb;
+
+       return ERROR_OK;
 }
 
-static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
+static int arm926ejs_disable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
-       jtag_execute_queue();
+       retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
        {
                /* invalidate TLB */
-               arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
+               retval = arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                cp15_control &= ~0x1U;
        }
@@ -369,17 +375,25 @@ static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
                uint32_t debug_override;
                /* read-modify-write CP15 debug override register
                 * to enable "test and clean all" */
-               arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
+               retval = arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
+               if (retval != ERROR_OK)
+                       return retval;
                debug_override |= 0x80000;
-               arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               if (retval != ERROR_OK)
+                       return retval;
 
                /* clean and invalidate DCache */
-               arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                /* write CP15 debug override register
                 * to disable "test and clean all" */
                debug_override &= ~0x80000;
-               arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+               if (retval != ERROR_OK)
+                       return retval;
 
                cp15_control &= ~0x4U;
        }
@@ -387,23 +401,31 @@ static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
        {
                /* invalidate ICache */
-               arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                cp15_control &= ~0x1000U;
        }
 
-       arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       return retval;
 }
 
-static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
+static int arm926ejs_enable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
-       jtag_execute_queue();
+       retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control |= 0x1U;
@@ -414,24 +436,34 @@ static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
                cp15_control |= 0x1000U;
 
-       arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+       return retval;
 }
 
-static void arm926ejs_post_debug_entry(struct target *target)
+static int arm926ejs_post_debug_entry(struct target *target)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
+       int retval;
 
        /* examine cp15 control reg */
-       arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
-       jtag_execute_queue();
+       retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
 
        if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
        {
                uint32_t cache_type_reg;
                /* identify caches */
-               arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
-               jtag_execute_queue();
+               retval = arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
                armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
        }
 
@@ -440,9 +472,15 @@ static void arm926ejs_post_debug_entry(struct target *target)
        arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 
        /* save i/d fault status and address register */
-       arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
-       arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
-       arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+       retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+       if (retval != ERROR_OK)
+               return retval;
 
        LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
                arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
@@ -451,9 +489,12 @@ static void arm926ejs_post_debug_entry(struct target *target)
 
        /* read-modify-write CP15 cache debug control register
         * to disable I/D-cache linefills and force WT */
-       arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+       retval = arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+       if (retval != ERROR_OK)
+               return retval;
        cache_dbg_ctrl |= 0x7;
-       arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+       retval = arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+       return retval;
 }
 
 static void arm926ejs_pre_restore_context(struct target *target)
@@ -495,7 +536,6 @@ int arm926ejs_arch_state(struct target *target)
        };
 
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
-       struct arm *armv4_5;
 
        if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
        {
@@ -503,8 +543,6 @@ int arm926ejs_arch_state(struct target *target)
                return ERROR_TARGET_INVALID;
        }
 
-       armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
-
        arm_arch_state(target);
        LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
                         state[arm926ejs->armv4_5_mmu.mmu_enabled],
@@ -573,7 +611,9 @@ int arm926ejs_soft_reset_halt(struct target *target)
        armv4_5->pc->dirty = 1;
        armv4_5->pc->valid = 1;
 
-       arm926ejs_disable_mmu_caches(target, 1, 1, 1);
+       retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
+       if (retval != ERROR_OK)
+               return retval;
        arm926ejs->armv4_5_mmu.mmu_enabled = 0;
        arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
        arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
@@ -583,14 +623,19 @@ int arm926ejs_soft_reset_halt(struct target *target)
 
 /** Writes a buffer, in the specified word size, with current MMU settings. */
 int arm926ejs_write_memory(struct target *target, uint32_t address,
-               uint32_t size, uint32_t count, uint8_t *buffer)
+               uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        int retval;
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
        /* FIX!!!! this should be cleaned up and made much more general. The
         * plan is to write up and test on arm926ejs specifically and
-        * then generalize and clean up afterwards. */
+        * then generalize and clean up afterwards.
+        *
+        *
+        * Also it should be moved to the callbacks that handle breakpoints
+        * specifically and not the generic memory write fn's. See XScale code.
+        **/
        if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
        {
                /* special case the handling of single word writes to bypass MMU
@@ -645,7 +690,7 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
 
 static int arm926ejs_write_phys_memory(struct target *target,
                uint32_t address, uint32_t size,
-               uint32_t count, uint8_t *buffer)
+               uint32_t count, const uint8_t *buffer)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
@@ -726,17 +771,14 @@ COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
 
 static int arm926ejs_virt2phys(struct target *target, uint32_t virtual, uint32_t *physical)
 {
-       int type;
        uint32_t cb;
-       int domain;
-       uint32_t ap;
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
-       uint32_t ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
-       if (type == -1)
-       {
-               return ret;
-       }
+       uint32_t ret;
+       int retval = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu,
+                       virtual, &cb, &ret);
+       if (retval != ERROR_OK)
+               return retval;
        *physical = ret;
        return ERROR_OK;
 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)