Fix "unused variable" warnings (errors) detected with GCC 4.7.0 - trivial fixes
[openocd.git] / src / target / arm926ejs.c
index f8a4f6294cfab20e91d5d38ad418f29ccf9eae31..873e9a033e73b7029a64b8014b7482a33b19e391 100644 (file)
@@ -67,7 +67,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
        {
                return retval;
        }
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
@@ -120,7 +122,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
        LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 #endif
 
-       arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        return ERROR_OK;
 }
@@ -155,7 +159,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
        {
                return retval;
        }
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 32;
        fields[0].out_value = value_buf;
@@ -205,7 +211,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
        LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 #endif
 
-       arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+       retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        return ERROR_OK;
 }
@@ -432,21 +440,30 @@ static int arm926ejs_enable_mmu_caches(struct target *target, int mmu,
        return retval;
 }
 
-static void arm926ejs_post_debug_entry(struct target *target)
+static int arm926ejs_post_debug_entry(struct target *target)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
+       int retval;
 
        /* examine cp15 control reg */
-       arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
-       jtag_execute_queue();
+       retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
 
        if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
        {
                uint32_t cache_type_reg;
                /* identify caches */
-               arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
-               jtag_execute_queue();
+               retval = arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
                armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
        }
 
@@ -455,9 +472,15 @@ static void arm926ejs_post_debug_entry(struct target *target)
        arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 
        /* save i/d fault status and address register */
-       arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
-       arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
-       arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+       retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+       if (retval != ERROR_OK)
+               return retval;
 
        LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
                arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
@@ -466,9 +489,12 @@ static void arm926ejs_post_debug_entry(struct target *target)
 
        /* read-modify-write CP15 cache debug control register
         * to disable I/D-cache linefills and force WT */
-       arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+       retval = arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+       if (retval != ERROR_OK)
+               return retval;
        cache_dbg_ctrl |= 0x7;
-       arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+       retval = arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+       return retval;
 }
 
 static void arm926ejs_pre_restore_context(struct target *target)
@@ -510,7 +536,6 @@ int arm926ejs_arch_state(struct target *target)
        };
 
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
-       struct arm *armv4_5;
 
        if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
        {
@@ -518,8 +543,6 @@ int arm926ejs_arch_state(struct target *target)
                return ERROR_TARGET_INVALID;
        }
 
-       armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
-
        arm_arch_state(target);
        LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
                         state[arm926ejs->armv4_5_mmu.mmu_enabled],
@@ -600,7 +623,7 @@ int arm926ejs_soft_reset_halt(struct target *target)
 
 /** Writes a buffer, in the specified word size, with current MMU settings. */
 int arm926ejs_write_memory(struct target *target, uint32_t address,
-               uint32_t size, uint32_t count, uint8_t *buffer)
+               uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        int retval;
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
@@ -667,7 +690,7 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
 
 static int arm926ejs_write_phys_memory(struct target *target,
                uint32_t address, uint32_t size,
-               uint32_t count, uint8_t *buffer)
+               uint32_t count, const uint8_t *buffer)
 {
        struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)