uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
uint32_t component_base;
unsigned part_num;
- char *type, *full;
+ const char *type, *full;
component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
if (((c_cid1 >> 4) & 0x0f) == 9) {
uint32_t devtype;
unsigned minor;
- char *major = "Reserved", *subtype = "Reserved";
+ const char *major = "Reserved", *subtype = "Reserved";
retval = mem_ap_read_atomic_u32(dap,
(component_base & 0xfffff000) | 0xfcc,
type = "Coresight ITM";
full = "(Instrumentation Trace Macrocell)";
break;
+ case 0x914:
+ type = "Coresight SWO";
+ full = "(Single Wire Output)";
+ break;
case 0x917:
type = "Coresight HTM";
full = "(AHB Trace Macrocell)";
type = "CoreSight Component";
full = "(unidentified Cortex-A9 component)";
break;
+ case 0x961:
+ type = "CoreSight TMC";
+ full = "(Trace Memory Controller)";
+ break;
case 0x962:
type = "CoreSight STM";
full = "(System Trace Macrocell)";
type = "Cortex-M4 TPUI";
full = "(Trace Port Interface Unit)";
break;
+ case 0x9a5:
+ type = "Cortex-A5 ETM";
+ full = "(Embedded Trace)";
+ break;
+ case 0xc05:
+ type = "Cortex-A5 Debug";
+ full = "(Debug Unit)";
+ break;
case 0xc08:
type = "Cortex-A8 Debug";
full = "(Debug Unit)";
type = "Cortex-A9 Debug";
full = "(Debug Unit)";
break;
+ case 0x4af:
+ type = "Cortex-A15 Debug";
+ full = "(Debug Unit)";
+ break;
default:
+ LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
type = "-*- unrecognized -*-";
full = "";
break;
command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
- if (romtable_present) {
+ if (romtable_present)
dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
- } else
+ else
command_print(cmd_ctx, "\tNo ROM table present");
dap_ap_select(dap, ap_old);