* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
/**
static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
{
- if (tar != ap->tar_value ||
- (ap->csw_value & CSW_ADDRINC_MASK)) {
+ if (!ap->tar_valid || tar != ap->tar_value) {
/* LOG_DEBUG("DAP: Set TAR %x",tar); */
int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
if (retval != ERROR_OK)
return retval;
ap->tar_value = tar;
+ ap->tar_valid = true;
}
return ERROR_OK;
}
+static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
+{
+ int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
+ if (retval != ERROR_OK) {
+ ap->tar_valid = false;
+ return retval;
+ }
+
+ retval = dap_run(ap->dap);
+ if (retval != ERROR_OK) {
+ ap->tar_valid = false;
+ return retval;
+ }
+
+ ap->tar_value = *tar;
+ ap->tar_valid = true;
+ return ERROR_OK;
+}
+
+static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
+{
+ switch (ap->csw_value & CSW_ADDRINC_MASK) {
+ case CSW_ADDRINC_SINGLE:
+ switch (ap->csw_value & CSW_SIZE_MASK) {
+ case CSW_8BIT:
+ return 1;
+ case CSW_16BIT:
+ return 2;
+ case CSW_32BIT:
+ return 4;
+ }
+ case CSW_ADDRINC_PACKED:
+ return 4;
+ }
+ return 0;
+}
+
+/* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
+ */
+static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
+{
+ if (!ap->tar_valid)
+ return;
+
+ uint32_t inc = mem_ap_get_tar_increment(ap);
+ if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
+ ap->tar_valid = false;
+ else
+ ap->tar_value += inc;
+}
+
/**
* Queue transactions setting up transfer parameters for the
* currently selected MEM-AP.
/* Use banked addressing (REG_BDx) to avoid some link traffic
* (updating TAR) when reading several consecutive addresses.
*/
- retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
+ retval = mem_ap_setup_transfer(ap,
+ CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
address & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
/* Use banked addressing (REG_BDx) to avoid some link traffic
* (updating TAR) when writing several consecutive addresses.
*/
- retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
+ retval = mem_ap_setup_transfer(ap,
+ CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
address & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
if (ap->unaligned_access_bad && (address % size != 0))
return ERROR_TARGET_UNALIGNED_ACCESS;
- retval = mem_ap_setup_tar(ap, address ^ addr_xor);
- if (retval != ERROR_OK)
- return retval;
-
while (nbytes > 0) {
uint32_t this_size = size;
if (retval != ERROR_OK)
break;
+ retval = mem_ap_setup_tar(ap, address ^ addr_xor);
+ if (retval != ERROR_OK)
+ return retval;
+
/* How many source bytes each transfer will consume, and their location in the DRW,
* depends on the type of transfer and alignment. See ARM document IHI0031C. */
uint32_t outvalue = 0;
+ uint32_t drw_byte_idx = address;
if (dap->ti_be_32_quirks) {
switch (this_size) {
case 4:
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
break;
case 2:
- outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
- outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
break;
case 1:
- outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
+ outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
break;
}
} else {
switch (this_size) {
case 4:
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
+ /* fallthrough */
case 2:
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
+ /* fallthrough */
case 1:
- outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
+ outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
}
}
if (retval != ERROR_OK)
break;
- /* Rewrite TAR if it wrapped or we're xoring addresses */
- if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
- retval = mem_ap_setup_tar(ap, address ^ addr_xor);
- if (retval != ERROR_OK)
- break;
- }
+ mem_ap_update_tar_cache(ap);
+ if (addrinc)
+ address += this_size;
}
/* REVISIT: Might want to have a queued version of this function that does not run. */
if (retval != ERROR_OK) {
uint32_t tar;
- if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
- && dap_run(dap) == ERROR_OK)
+ if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
else
LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
return ERROR_FAIL;
}
- retval = mem_ap_setup_tar(ap, address);
- if (retval != ERROR_OK) {
- free(read_buf);
- return retval;
- }
-
/* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
* useful bytes it contains, and their location in the word, depends on the type of transfer
* and alignment. */
if (retval != ERROR_OK)
break;
+ retval = mem_ap_setup_tar(ap, address);
+ if (retval != ERROR_OK)
+ break;
+
retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
if (retval != ERROR_OK)
break;
nbytes -= this_size;
- address += this_size;
+ if (addrinc)
+ address += this_size;
- /* Rewrite TAR if it wrapped */
- if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
- retval = mem_ap_setup_tar(ap, address);
- if (retval != ERROR_OK)
- break;
- }
+ mem_ap_update_tar_cache(ap);
}
if (retval == ERROR_OK)
* at least give the caller what we have. */
if (retval != ERROR_OK) {
uint32_t tar;
- if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
- && dap_run(dap) == ERROR_OK) {
+ if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
+ /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
if (nbytes > tar - address)
nbytes = tar - address;
case 4:
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
+ /* fallthrough */
case 2:
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
+ /* fallthrough */
case 1:
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
}
case 4:
*buffer++ = *read_ptr >> 8 * (address++ & 3);
*buffer++ = *read_ptr >> 8 * (address++ & 3);
+ /* fallthrough */
case 2:
*buffer++ = *read_ptr >> 8 * (address++ & 3);
+ /* fallthrough */
case 1:
*buffer++ = *read_ptr >> 8 * (address++ & 3);
}
return dap;
}
+/**
+ * Invalidate cached DP select and cached TAR and CSW of all APs
+ */
+void dap_invalidate_cache(struct adiv5_dap *dap)
+{
+ dap->select = DP_SELECT_INVALID;
+ dap->last_read = NULL;
+
+ int i;
+ for (i = 0; i <= 255; i++) {
+ /* force csw and tar write on the next mem-ap access */
+ dap->ap[i].tar_valid = false;
+ dap->ap[i].csw_value = 0;
+ }
+}
+
/**
* Initialize a DAP. This sets up the power domains, prepares the DP
* for further use and activates overrun checking.
if (!dap->ops)
dap->ops = &jtag_dp_ops;
- dap->select = DP_SELECT_INVALID;
- dap->last_read = NULL;
+ dap_invalidate_cache(dap);
- for (size_t i = 0; i < 10; i++) {
+ for (size_t i = 0; i < 30; i++) {
/* DP initialization */
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- continue;
-
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
- if (retval != ERROR_OK)
- continue;
+ retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
+ if (retval == ERROR_OK)
+ break;
+ }
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- continue;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
+ if (retval != ERROR_OK)
+ return retval;
- dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
- if (retval != ERROR_OK)
- continue;
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
+ if (retval != ERROR_OK)
+ return retval;
- /* Check that we have debug power domains activated */
- LOG_DEBUG("DAP: wait CDBGPWRUPACK");
- retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
- CDBGPWRUPACK, CDBGPWRUPACK,
- DAP_POWER_DOMAIN_TIMEOUT);
- if (retval != ERROR_OK)
- continue;
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
+ if (retval != ERROR_OK)
+ return retval;
- LOG_DEBUG("DAP: wait CSYSPWRUPACK");
- retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
- CSYSPWRUPACK, CSYSPWRUPACK,
- DAP_POWER_DOMAIN_TIMEOUT);
- if (retval != ERROR_OK)
- continue;
+ /* Check that we have debug power domains activated */
+ LOG_DEBUG("DAP: wait CDBGPWRUPACK");
+ retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
+ CDBGPWRUPACK, CDBGPWRUPACK,
+ DAP_POWER_DOMAIN_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- continue;
+ LOG_DEBUG("DAP: wait CSYSPWRUPACK");
+ retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
+ CSYSPWRUPACK, CSYSPWRUPACK,
+ DAP_POWER_DOMAIN_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
- /* With debug power on we can activate OVERRUN checking */
- dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
- if (retval != ERROR_OK)
- continue;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
- if (retval != ERROR_OK)
- continue;
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
+ if (retval != ERROR_OK)
+ return retval;
- retval = dap_run(dap);
- if (retval != ERROR_OK)
- continue;
+ /* With debug power on we can activate OVERRUN checking */
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
+ if (retval != ERROR_OK)
+ return retval;
- break;
- }
+ retval = dap_run(dap);
+ if (retval != ERROR_OK)
+ return retval;
return retval;
}
int retval;
struct adiv5_dap *dap = ap->dap;
+ ap->tar_valid = false;
+ ap->csw_value = 0; /* force csw and tar write */
retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
if (retval != ERROR_OK)
return retval;
{ ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
+ { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
{ 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
{ 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
{ 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
int retval;
uint64_t pid;
uint32_t cid;
- char tabs[7] = "";
+ char tabs[16] = "";
if (depth > 16) {
command_print(cmd_ctx, "\tTables too deep");
return ERROR_OK;
}
+int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
+{
+ struct adiv5_private_config *pc;
+ const char *arg;
+ jim_wide ap_num;
+ int e;
+
+ /* check if argv[0] is for us */
+ arg = Jim_GetString(goi->argv[0], NULL);
+ if (strcmp(arg, "-ap-num"))
+ return JIM_CONTINUE;
+
+ e = Jim_GetOpt_String(goi, &arg, NULL);
+ if (e != JIM_OK)
+ return e;
+
+ if (goi->argc == 0) {
+ Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-ap-num ?ap-number? ...");
+ return JIM_ERR;
+ }
+
+ e = Jim_GetOpt_Wide(goi, &ap_num);
+ if (e != JIM_OK)
+ return e;
+
+ if (target->private_config == NULL) {
+ pc = calloc(1, sizeof(struct adiv5_private_config));
+ target->private_config = pc;
+ pc->ap_num = ap_num;
+ }
+
+
+ return JIM_OK;
+}
+
COMMAND_HANDLER(handle_dap_info_command)
{
struct target *target = get_current_target(CMD_CTX);
return retval;
}
+COMMAND_HANDLER(dap_apreg_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm *arm = target_to_arm(target);
+ struct adiv5_dap *dap = arm->dap;
+
+ uint32_t apsel, reg, value;
+ int retval;
+
+ if (CMD_ARGC < 2 || CMD_ARGC > 3)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
+ if (reg >= 256 || (reg & 3))
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (CMD_ARGC == 3) {
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
+ retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
+ } else {
+ retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
+ }
+ if (retval == ERROR_OK)
+ retval = dap_run(dap);
+
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (CMD_ARGC == 2)
+ command_print(CMD_CTX, "0x%08" PRIx32, value);
+
+ return retval;
+}
+
COMMAND_HANDLER(dap_ti_be_32_quirks_command)
{
struct target *target = get_current_target(CMD_CTX);
"(default currently selected AP)",
.usage = "[ap_num]",
},
+ {
+ .name = "apreg",
+ .handler = dap_apreg_command,
+ .mode = COMMAND_EXEC,
+ .help = "read/write a register from AP "
+ "(reg is byte address of a word register, like 0 4 8...)",
+ .usage = "ap_num reg [value]",
+ },
{
.name = "baseaddr",
.handler = dap_baseaddr_command,