return mem_ap_write(swjdp, buffer, size, count, address, false);
}
-#define MDM_REG_STAT 0x00
-#define MDM_REG_CTRL 0x04
-#define MDM_REG_ID 0xfc
-
-#define MDM_STAT_FMEACK (1<<0)
-#define MDM_STAT_FREADY (1<<1)
-#define MDM_STAT_SYSSEC (1<<2)
-#define MDM_STAT_SYSRES (1<<3)
-#define MDM_STAT_FMEEN (1<<5)
-#define MDM_STAT_BACKDOOREN (1<<6)
-#define MDM_STAT_LPEN (1<<7)
-#define MDM_STAT_VLPEN (1<<8)
-#define MDM_STAT_LLSMODEXIT (1<<9)
-#define MDM_STAT_VLLSXMODEXIT (1<<10)
-#define MDM_STAT_CORE_HALTED (1<<16)
-#define MDM_STAT_CORE_SLEEPDEEP (1<<17)
-#define MDM_STAT_CORESLEEPING (1<<18)
-
-#define MEM_CTRL_FMEIP (1<<0)
-#define MEM_CTRL_DBG_DIS (1<<1)
-#define MEM_CTRL_DBG_REQ (1<<2)
-#define MEM_CTRL_SYS_RES_REQ (1<<3)
-#define MEM_CTRL_CORE_HOLD_RES (1<<4)
-#define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
-#define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
-#define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
-
-#define MDM_ACCESS_TIMEOUT 3000 /* ms */
-
-/**
- *
- */
-int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
-{
- uint32_t val;
- int retval;
- int timeout = 0;
- enum reset_types jtag_reset_config = jtag_get_reset_config();
-
- dap_ap_select(dap, 1);
-
- /* first check mdm-ap id register */
- retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
- if (retval != ERROR_OK)
- return retval;
- dap_run(dap);
-
- if (val != 0x001C0000) {
- LOG_DEBUG("id doesn't match %08" PRIX32 " != 0x001C0000", val);
- dap_ap_select(dap, 0);
- return ERROR_FAIL;
- }
-
- /* read and parse status register
- * it's important that the device is out of
- * reset here
- */
- while (1) {
- if (timeout++ > MDM_ACCESS_TIMEOUT) {
- LOG_DEBUG("MDMAP : flash ready timeout");
- return ERROR_FAIL;
- }
- retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
- if (retval != ERROR_OK)
- return retval;
- dap_run(dap);
-
- LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
- if (val & MDM_STAT_FREADY)
- break;
- alive_sleep(1);
- }
-
- if ((val & MDM_STAT_SYSSEC)) {
- LOG_DEBUG("MDMAP: system is secured, masserase needed");
-
- if (!(val & MDM_STAT_FMEEN))
- LOG_DEBUG("MDMAP: masserase is disabled");
- else {
- /* we need to assert reset */
- if (jtag_reset_config & RESET_HAS_SRST) {
- /* default to asserting srst */
- adapter_assert_reset();
- } else {
- LOG_DEBUG("SRST not configured");
- dap_ap_select(dap, 0);
- return ERROR_FAIL;
- }
- timeout = 0;
- while (1) {
- if (timeout++ > MDM_ACCESS_TIMEOUT) {
- LOG_DEBUG("MDMAP : flash ready timeout");
- return ERROR_FAIL;
- }
- retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
- if (retval != ERROR_OK)
- return retval;
- dap_run(dap);
- /* read status register and wait for ready */
- retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
- if (retval != ERROR_OK)
- return retval;
- dap_run(dap);
- LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
-
- if ((val & 1))
- break;
- alive_sleep(1);
- }
- timeout = 0;
- while (1) {
- if (timeout++ > MDM_ACCESS_TIMEOUT) {
- LOG_DEBUG("MDMAP : flash ready timeout");
- return ERROR_FAIL;
- }
- retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
- if (retval != ERROR_OK)
- return retval;
- dap_run(dap);
- /* read status register */
- retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
- if (retval != ERROR_OK)
- return retval;
- dap_run(dap);
- LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
- /* read control register and wait for ready */
- retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
- if (retval != ERROR_OK)
- return retval;
- dap_run(dap);
- LOG_DEBUG("MDM_REG_CTRL %08" PRIX32, val);
-
- if (val == 0x00)
- break;
- alive_sleep(1);
- }
- }
- }
-
- dap_ap_select(dap, 0);
-
- return ERROR_OK;
-}
-
-/** */
-struct dap_syssec_filter {
- /** */
- uint32_t idcode;
- /** */
- int (*dap_init)(struct adiv5_dap *dap);
-};
-
-/** */
-static struct dap_syssec_filter dap_syssec_filter_data[] = {
- { 0x4BA00477, dap_syssec_kinetis_mdmap }
-};
-
-/**
- *
- */
-int dap_syssec(struct adiv5_dap *dap)
-{
- unsigned int i;
- struct jtag_tap *tap;
-
- for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
- tap = dap->jtag_info->tap;
-
- while (tap != NULL) {
- if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
- LOG_DEBUG("DAP: mdmap_init for idcode: %08" PRIx32, tap->idcode);
- dap_syssec_filter_data[i].dap_init(dap);
- }
- tap = tap->next_tap;
- }
- }
-
- return ERROR_OK;
-}
-
/*--------------------------------------------------------------------------*/
+#define DAP_POWER_DOMAIN_TIMEOUT (10)
+
/* FIXME don't import ... just initialize as
* part of DAP transport setup
*/
*/
int ahbap_debugport_init(struct adiv5_dap *dap)
{
- uint32_t ctrlstat;
- int cnt = 0;
int retval;
LOG_DEBUG(" ");
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
+ /* Check that we have debug power domains activated */
+ LOG_DEBUG("DAP: wait CDBGPWRUPACK");
+ retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
+ CDBGPWRUPACK, CDBGPWRUPACK,
+ DAP_POWER_DOMAIN_TIMEOUT);
if (retval != ERROR_OK)
return retval;
- retval = dap_run(dap);
+
+ LOG_DEBUG("DAP: wait CSYSPWRUPACK");
+ retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
+ CSYSPWRUPACK, CSYSPWRUPACK,
+ DAP_POWER_DOMAIN_TIMEOUT);
if (retval != ERROR_OK)
return retval;
- /* Check that we have debug power domains activated */
- while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
- LOG_DEBUG("DAP: wait CDBGPWRUPACK");
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
- if (retval != ERROR_OK)
- return retval;
- retval = dap_run(dap);
- if (retval != ERROR_OK)
- return retval;
- alive_sleep(10);
- }
-
- while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
- LOG_DEBUG("DAP: wait CSYSPWRUPACK");
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
- if (retval != ERROR_OK)
- return retval;
- retval = dap_run(dap);
- if (retval != ERROR_OK)
- return retval;
- alive_sleep(10);
- }
-
retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- dap_syssec(dap);
-
/* check that we support packed transfers */
uint32_t csw, cfg;
"start address 0x%" PRIx32, component_base,
/* component may take multiple 4K pages */
(uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
- command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
- (c_cid1 >> 4) & 0xf,
+ command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
+ (uint8_t)((c_cid1 >> 4) & 0xf),
/* See ARM IHI 0029B Table 3-3 */
class_description[(c_cid1 >> 4) & 0xf]);
case 2:
subtype = "Buffer";
break;
+ case 3:
+ subtype = "Router";
+ break;
}
break;
case 2:
case 4:
subtype = "Bus";
break;
+ case 6:
+ subtype = "Software";
+ break;
}
break;
case 4:
case 2:
subtype = "Debug Auth";
break;
+ case 3:
+ subtype = "Power Requestor";
+ break;
}
break;
case 5:
case 3:
subtype = "Engine/Coprocessor";
break;
+ case 4:
+ subtype = "Bus";
+ break;
+ case 5:
+ subtype = "Memory";
+ break;
+ }
+ break;
+ case 6:
+ major = "Perfomance Monitor";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Processor";
+ break;
+ case 2:
+ subtype = "DSP";
+ break;
+ case 3:
+ subtype = "Engine/Coprocessor";
+ break;
+ case 4:
+ subtype = "Bus";
+ break;
+ case 5:
+ subtype = "Memory";
+ break;
}
break;
}
- command_print(cmd_ctx, "\t\tType is 0x%02x, %s, %s",
- devtype & 0xff,
+ command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
+ (uint8_t)(devtype & 0xff),
major, subtype);
/* REVISIT also show 0xfc8 DevId */
}
type = "Coresight ITM";
full = "(Instrumentation Trace Macrocell)";
break;
+ case 0x917:
+ type = "Coresight HTM";
+ full = "(AHB Trace Macrocell)";
+ break;
+ case 0x920:
+ type = "CoreSight ETM11";
+ full = "(Embedded Trace)";
+ break;
case 0x921:
type = "Cortex-A8 ETM";
full = "(Embedded Trace)";
type = "CoreSight Component";
full = "(unidentified Cortex-A9 component)";
break;
+ case 0x962:
+ type = "CoreSight STM";
+ full = "(System Trace Macrocell)";
+ break;
case 0x9a0:
type = "CoreSight PMU";
full = "(Performance Monitoring Unit)";
Code Review / openocd.git / blobdiff