*/
int dap_to_swd(struct adiv5_dap *dap)
{
- int retval;
-
LOG_DEBUG("Enter SWD mode");
- if (transport_is_jtag()) {
- retval = jtag_add_tms_seq(swd_seq_jtag_to_swd_len,
- swd_seq_jtag_to_swd, TAP_INVALID);
- if (retval == ERROR_OK)
- retval = jtag_execute_queue();
- return retval;
- }
-
- if (transport_is_swd()) {
- const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
-
- return swd->switch_seq(JTAG_TO_SWD);
- }
-
- LOG_ERROR("Nor JTAG nor SWD transport");
- return ERROR_FAIL;
+ return dap_send_sequence(dap, JTAG_TO_SWD);
}
/**
*/
int dap_to_jtag(struct adiv5_dap *dap)
{
- int retval;
-
LOG_DEBUG("Enter JTAG mode");
- if (transport_is_jtag()) {
- retval = jtag_add_tms_seq(swd_seq_swd_to_jtag_len,
- swd_seq_swd_to_jtag, TAP_RESET);
- if (retval == ERROR_OK)
- retval = jtag_execute_queue();
- return retval;
- }
-
- if (transport_is_swd()) {
- const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
-
- return swd->switch_seq(SWD_TO_JTAG);
- }
-
- LOG_ERROR("Nor JTAG nor SWD transport");
- return ERROR_FAIL;
+ return dap_send_sequence(dap, SWD_TO_JTAG);
}
/* CID interpretation -- see ARM IHI 0029B section 3
((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
- (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
+ (type_to_find == AP_TYPE_AHB3_AP) ? "AHB3-AP" :
+ (type_to_find == AP_TYPE_AHB5_AP) ? "AHB5-AP" :
(type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
(type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
(type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
}
LOG_DEBUG("No %s found",
- (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
+ (type_to_find == AP_TYPE_AHB3_AP) ? "AHB3-AP" :
+ (type_to_find == AP_TYPE_AHB5_AP) ? "AHB5-AP" :
(type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
(type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
(type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
{ ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
{ ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
{ ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
+ { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
+ { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
{ ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
{ ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
{ ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
{ ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
{ ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
{ ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
{ ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
{ ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
- { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
- { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
- { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
{ ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
{ ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
{ ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
{ 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
{ 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
{ 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
- { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
{ 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
+ { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
{ 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
{ 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
/* legacy comment: 0x113: what? */
{ ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
};
-static int dap_rom_display(struct command_context *cmd_ctx,
+static int dap_rom_display(struct command_invocation *cmd,
struct adiv5_ap *ap, uint32_t dbgbase, int depth)
{
int retval;
char tabs[16] = "";
if (depth > 16) {
- command_print(cmd_ctx, "\tTables too deep");
+ command_print(cmd, "\tTables too deep");
return ERROR_FAIL;
}
snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
uint32_t base_addr = dbgbase & 0xFFFFF000;
- command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
+ command_print(cmd, "\t\tComponent base address 0x%08" PRIx32, base_addr);
retval = dap_read_part_id(ap, base_addr, &cid, &pid);
if (retval != ERROR_OK) {
- command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
+ command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
return ERROR_OK; /* Don't abort recursion */
}
if (!is_dap_cid_ok(cid)) {
- command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
+ command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, cid);
return ERROR_OK; /* Don't abort recursion */
}
/* component may take multiple 4K pages */
uint32_t size = (pid >> 36) & 0xf;
if (size > 0)
- command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
+ command_print(cmd, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
- command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
+ command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
uint8_t class = (cid >> 12) & 0xf;
uint16_t part_num = pid & 0xfff;
if (designer_id & 0x80) {
/* JEP106 code */
- command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
+ command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
} else {
/* Legacy ASCII ID, clear invalid bits */
designer_id &= 0x7f;
- command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
+ command_print(cmd, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
}
break;
}
- command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
- command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
+ command_print(cmd, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
+ command_print(cmd, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
if (class == 1) { /* ROM Table */
uint32_t memtype;
return retval;
if (memtype & 0x01)
- command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
+ command_print(cmd, "\t\tMEMTYPE system memory present on bus");
else
- command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
+ command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
- command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
+ command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
tabs, entry_offset, romentry);
if (romentry & 0x01) {
/* Recurse */
- retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
+ retval = dap_rom_display(cmd, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
if (retval != ERROR_OK)
return retval;
} else if (romentry != 0) {
- command_print(cmd_ctx, "\t\tComponent not present");
+ command_print(cmd, "\t\tComponent not present");
} else {
- command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
+ command_print(cmd, "\t%s\tEnd of ROM table", tabs);
break;
}
}
}
break;
case 6:
- major = "Perfomance Monitor";
+ major = "Performance Monitor";
switch (minor) {
case 0:
subtype = "other";
}
break;
}
- command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
+ command_print(cmd, "\t\tType is 0x%02" PRIx8 ", %s, %s",
(uint8_t)(devtype & 0xff),
major, subtype);
/* REVISIT also show 0xfc8 DevId */
return ERROR_OK;
}
-int dap_info_command(struct command_context *cmd_ctx,
+int dap_info_command(struct command_invocation *cmd,
struct adiv5_ap *ap)
{
int retval;
if (retval != ERROR_OK)
return retval;
- command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
+ command_print(cmd, "AP ID register 0x%8.8" PRIx32, apid);
if (apid == 0) {
- command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
+ command_print(cmd, "No AP found at this ap 0x%x", ap->ap_num);
return ERROR_FAIL;
}
switch (apid & (IDR_JEP106 | IDR_TYPE)) {
case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
- command_print(cmd_ctx, "\tType is JTAG-AP");
+ command_print(cmd, "\tType is JTAG-AP");
break;
- case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
- command_print(cmd_ctx, "\tType is MEM-AP AHB");
+ case IDR_JEP106_ARM | AP_TYPE_AHB3_AP:
+ command_print(cmd, "\tType is MEM-AP AHB3");
+ break;
+ case IDR_JEP106_ARM | AP_TYPE_AHB5_AP:
+ command_print(cmd, "\tType is MEM-AP AHB5");
break;
case IDR_JEP106_ARM | AP_TYPE_APB_AP:
- command_print(cmd_ctx, "\tType is MEM-AP APB");
+ command_print(cmd, "\tType is MEM-AP APB");
break;
case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
- command_print(cmd_ctx, "\tType is MEM-AP AXI");
+ command_print(cmd, "\tType is MEM-AP AXI");
break;
default:
- command_print(cmd_ctx, "\tUnknown AP type");
+ command_print(cmd, "\tUnknown AP type");
break;
}
*/
mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
if (mem_ap) {
- command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
+ command_print(cmd, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
- command_print(cmd_ctx, "\tNo ROM table present");
+ command_print(cmd, "\tNo ROM table present");
} else {
if (dbgbase & 0x01)
- command_print(cmd_ctx, "\tValid ROM table present");
+ command_print(cmd, "\tValid ROM table present");
else
- command_print(cmd_ctx, "\tROM table in legacy format");
+ command_print(cmd, "\tROM table in legacy format");
- dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
+ dap_rom_display(cmd, ap, dbgbase & 0xFFFFF000, 0);
}
}
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
- if (apsel > DP_APSEL_MAX)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (apsel > DP_APSEL_MAX) {
+ command_print(CMD, "Invalid AP number");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
}
- return dap_info_command(CMD_CTX, &dap->ap[apsel]);
+ return dap_info_command(CMD, &dap->ap[apsel]);
}
COMMAND_HANDLER(dap_baseaddr_command)
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel > DP_APSEL_MAX)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (apsel > DP_APSEL_MAX) {
+ command_print(CMD, "Invalid AP number");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
if (retval != ERROR_OK)
return retval;
- command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
+ command_print(CMD, "0x%8.8" PRIx32, baseaddr);
return retval;
}
}
dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
- command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
+ command_print(CMD, "memory bus access delay set to %" PRIi32 " tck",
dap->ap[dap->apsel].memaccess_tck);
return ERROR_OK;
switch (CMD_ARGC) {
case 0:
- command_print(CMD_CTX, "%" PRIi32, dap->apsel);
+ command_print(CMD, "%" PRIi32, dap->apsel);
return ERROR_OK;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel > DP_APSEL_MAX)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (apsel > DP_APSEL_MAX) {
+ command_print(CMD, "Invalid AP number");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
switch (CMD_ARGC) {
case 0:
- command_print(CMD_CTX, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
+ command_print(CMD, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
dap->apsel, apcsw);
return ERROR_OK;
case 1:
if (strcmp(CMD_ARGV[0], "default") == 0)
- csw_val = CSW_DEFAULT;
+ csw_val = CSW_AHB_DEFAULT;
else
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
- return ERROR_COMMAND_SYNTAX_ERROR;
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
apcsw = csw_val;
break;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
- return ERROR_COMMAND_SYNTAX_ERROR;
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel > DP_APSEL_MAX)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (apsel > DP_APSEL_MAX) {
+ command_print(CMD, "Invalid AP number");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
if (retval != ERROR_OK)
return retval;
- command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
+ command_print(CMD, "0x%8.8" PRIx32, apid);
return retval;
}
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel > DP_APSEL_MAX)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (apsel > DP_APSEL_MAX) {
+ command_print(CMD, "Invalid AP number");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
+
ap = dap_ap(dap, apsel);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
- if (reg >= 256 || (reg & 3))
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (reg >= 256 || (reg & 3)) {
+ command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
if (CMD_ARGC == 3) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
return retval;
if (CMD_ARGC == 2)
- command_print(CMD_CTX, "0x%08" PRIx32, value);
+ command_print(CMD, "0x%08" PRIx32, value);
return retval;
}
return ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg);
- if (reg >= 256 || (reg & 3))
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (reg >= 256 || (reg & 3)) {
+ command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
if (CMD_ARGC == 2) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
return retval;
if (CMD_ARGC == 1)
- command_print(CMD_CTX, "0x%08" PRIx32, value);
+ command_print(CMD, "0x%08" PRIx32, value);
return retval;
}
COMMAND_HANDLER(dap_ti_be_32_quirks_command)
{
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
- uint32_t enable = dap->ti_be_32_quirks;
-
- switch (CMD_ARGC) {
- case 0:
- break;
- case 1:
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
- if (enable > 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
- break;
- default:
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
- dap->ti_be_32_quirks = enable;
- command_print(CMD_CTX, "TI BE-32 quirks mode %s",
- enable ? "enabled" : "disabled");
-
- return 0;
+ return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->ti_be_32_quirks,
+ "TI BE-32 quirks mode");
}
const struct command_registration dap_instance_commands[] = {
Code Review / openocd.git / blobdiff