src/target/arm_adi_v5.c: resorted ids

[openocd.git] / src / target / arm_adi_v5.c

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 5f6f1ff38e7dfab893ce760c258167f0089fa0df..241c00b0434fede0fb4ead9d10c151cdda08b000 100644 (file)
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1072,6 +1072,8 @@ static const struct {
        { ARM_ID, 0x00c, "Cortex-M4 SCS",              "(System Control Space)", },
        { ARM_ID, 0x00d, "CoreSight ETM11",            "(Embedded Trace)", },
        { ARM_ID, 0x00e, "Cortex-M7 FPB",              "(Flash Patch and Breakpoint)", },
+       { ARM_ID, 0x470, "Cortex-M1 ROM",              "(ROM Table)", },
+       { ARM_ID, 0x471, "Cortex-M0 ROM",              "(ROM Table)", },
        { ARM_ID, 0x490, "Cortex-A15 GIC",             "(Generic Interrupt Controller)", },
        { ARM_ID, 0x4a1, "Cortex-A53 ROM",             "(v8 Memory Map ROM Table)", },
        { ARM_ID, 0x4a2, "Cortex-A57 ROM",             "(ROM Table)", },
@@ -1079,14 +1081,12 @@ static const struct {
        { ARM_ID, 0x4a4, "Cortex-A72 ROM",             "(ROM Table)", },
        { ARM_ID, 0x4a9, "Cortex-A9 ROM",              "(ROM Table)", },
        { ARM_ID, 0x4af, "Cortex-A15 ROM",             "(ROM Table)", },
+       { ARM_ID, 0x4b5, "Cortex-R5 ROM",              "(ROM Table)", },
        { ARM_ID, 0x4c0, "Cortex-M0+ ROM",             "(ROM Table)", },
        { ARM_ID, 0x4c3, "Cortex-M3 ROM",              "(ROM Table)", },
        { ARM_ID, 0x4c4, "Cortex-M4 ROM",              "(ROM Table)", },
        { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM",          "(Private Peripheral Bus ROM Table)", },
        { ARM_ID, 0x4c8, "Cortex-M7 ROM",              "(ROM Table)", },
-       { ARM_ID, 0x4b5, "Cortex-R5 ROM",              "(ROM Table)", },
-       { ARM_ID, 0x470, "Cortex-M1 ROM",              "(ROM Table)", },
-       { ARM_ID, 0x471, "Cortex-M0 ROM",              "(ROM Table)", },
        { ARM_ID, 0x906, "CoreSight CTI",              "(Cross Trigger)", },
        { ARM_ID, 0x907, "CoreSight ETB",              "(Trace Buffer)", },
        { ARM_ID, 0x908, "CoreSight CSTF",             "(Trace Funnel)", },
@@ -1149,8 +1149,8 @@ static const struct {
        { 0x0E5,  0x000, "SHARC+/Blackfin+",           "", },
        { 0x0F0,  0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
        { 0x3eb,  0x181, "Tegra 186 ROM",              "(ROM Table)", },
-       { 0x3eb,  0x211, "Tegra 210 ROM",              "(ROM Table)", },
        { 0x3eb,  0x202, "Denver ETM",                 "(Denver Embedded Trace)", },
+       { 0x3eb,  0x211, "Tegra 210 ROM",              "(ROM Table)", },
        { 0x3eb,  0x302, "Denver Debug",               "(Debug Unit)", },
        { 0x3eb,  0x402, "Denver PMU",                 "(Performance Monitor Unit)", },
        /* legacy comment: 0x113: what? */
@@ -1878,24 +1878,8 @@ COMMAND_HANDLER(dap_dpreg_command)
 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
 {
        struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
-       uint32_t enable = dap->ti_be_32_quirks;
-
-       switch (CMD_ARGC) {
-       case 0:
-               break;
-       case 1:
-               COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
-               if (enable > 1)
-                       return ERROR_COMMAND_ARGUMENT_INVALID;
-               break;
-       default:
-               return ERROR_COMMAND_SYNTAX_ERROR;
-       }
-       dap->ti_be_32_quirks = enable;
-       command_print(CMD, "TI BE-32 quirks mode %s",
-               enable ? "enabled" : "disabled");
-
-       return 0;
+       return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->ti_be_32_quirks,
+               "TI BE-32 quirks mode");
 }
 
 const struct command_registration dap_instance_commands[] = {