* Copyright (C) 2013 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* *
+ * Copyright (C) 2019-2021, Ampere Computing LLC *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* This file implements support for the ARM Debug Interface version 5 (ADIv5)
* debugging architecture. Compared with previous versions, this includes
* a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
- * transport, and focusses on memory mapped resources as defined by the
+ * transport, and focuses on memory mapped resources as defined by the
* CoreSight architecture.
*
* A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
* is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
* further AP operations will fail. There are two basic methods to avoid
* such overrun errors. One involves polling for status instead of using
- * transaction piplining. The other involves adding delays to ensure the
+ * transaction pipelining. The other involves adding delays to ensure the
* AP has enough time to complete one operation before starting the next
* one. (For JTAG these delays are controlled by memaccess_tck.)
*/
/*
* Relevant specifications from ARM include:
*
- * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
+ * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
* CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
*
* CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
#include "jtag/interface.h"
#include "arm.h"
#include "arm_adi_v5.h"
+#include "jtag/swd.h"
+#include "transport/transport.h"
#include <helper/jep106.h>
#include <helper/time_support.h>
#include <helper/list.h>
+#include <helper/jim-nvp.h>
/* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
uint32_t tar_block_size(uint32_t address)
Return the largest block starting at address that does not cross a tar block size alignment boundary
*/
-static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
+static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, target_addr_t address)
{
return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
}
static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
{
- csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
- ap->csw_default;
+ csw |= ap->csw_default;
if (csw != ap->csw_value) {
/* LOG_DEBUG("DAP: Set CSW %x",csw); */
int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ ap->csw_value = 0;
return retval;
+ }
ap->csw_value = csw;
}
return ERROR_OK;
}
-static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
+static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
{
if (!ap->tar_valid || tar != ap->tar_value) {
/* LOG_DEBUG("DAP: Set TAR %x",tar); */
- int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
- if (retval != ERROR_OK)
+ int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, (uint32_t)(tar & 0xffffffffUL));
+ if (retval == ERROR_OK && is_64bit_ap(ap)) {
+ /* See if bits 63:32 of tar is different from last setting */
+ if ((ap->tar_value >> 32) != (tar >> 32))
+ retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64, (uint32_t)(tar >> 32));
+ }
+ if (retval != ERROR_OK) {
+ ap->tar_valid = false;
return retval;
+ }
ap->tar_value = tar;
ap->tar_valid = true;
}
return ERROR_OK;
}
-static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
+static int mem_ap_read_tar(struct adiv5_ap *ap, target_addr_t *tar)
{
- int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
+ uint32_t lower;
+ uint32_t upper = 0;
+
+ int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, &lower);
+ if (retval == ERROR_OK && is_64bit_ap(ap))
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR64, &upper);
+
if (retval != ERROR_OK) {
ap->tar_valid = false;
return retval;
return retval;
}
+ *tar = (((target_addr_t)upper) << 32) | (target_addr_t)lower;
+
ap->tar_value = *tar;
ap->tar_valid = true;
return ERROR_OK;
return 2;
case CSW_32BIT:
return 4;
+ default:
+ return 0;
}
case CSW_ADDRINC_PACKED:
return 4;
*
* @return ERROR_OK if the transaction was properly queued, else a fault code.
*/
-static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
+static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, target_addr_t tar)
{
int retval;
retval = mem_ap_setup_csw(ap, csw);
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
-int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
+int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t *value)
{
int retval;
*/
retval = mem_ap_setup_transfer(ap,
CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
- address & 0xFFFFFFF0);
+ address & 0xFFFFFFFFFFFFFFF0ull);
if (retval != ERROR_OK)
return retval;
* @return ERROR_OK for success; *value holds the result.
* Otherwise a fault code.
*/
-int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
+int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t *value)
{
int retval;
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
-int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
+int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t value)
{
int retval;
*/
retval = mem_ap_setup_transfer(ap,
CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
- address & 0xFFFFFFF0);
+ address & 0xFFFFFFFFFFFFFFF0ull);
if (retval != ERROR_OK)
return retval;
*
* @return ERROR_OK for success; the data was written. Otherwise a fault code.
*/
-int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
+int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t value)
{
int retval = mem_ap_write_u32(ap, address, value);
* @return ERROR_OK on success, otherwise an error code.
*/
static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
- uint32_t address, bool addrinc)
+ target_addr_t address, bool addrinc)
{
struct adiv5_dap *dap = ap->dap;
size_t nbytes = size * count;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
- uint32_t addr_xor;
- int retval;
+ target_addr_t addr_xor;
+ int retval = ERROR_OK;
/* TI BE-32 Quirks mode:
* Writes on big-endian TMS570 behave very strangely. Observed behavior:
retval = dap_run(dap);
if (retval != ERROR_OK) {
- uint32_t tar;
+ target_addr_t tar;
if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
- LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
+ LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT, tar);
else
LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
}
* @param buffer The data buffer to receive the data. No particular alignment is assumed.
* @param size Which access size to use, in bytes. 1, 2 or 4.
* @param count The number of reads to do (in size units, not bytes).
- * @param address Address to be read; it must be readable by the currently selected MEM-AP.
+ * @param adr Address to be read; it must be readable by the currently selected MEM-AP.
* @param addrinc Whether the target address should be increased after each read or not. This
* should normally be true, except when reading from e.g. a FIFO.
* @return ERROR_OK on success, otherwise an error code.
*/
static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
- uint32_t adr, bool addrinc)
+ target_addr_t adr, bool addrinc)
{
struct adiv5_dap *dap = ap->dap;
size_t nbytes = size * count;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
- uint32_t address = adr;
- int retval;
+ target_addr_t address = adr;
+ int retval = ERROR_OK;
/* TI BE-32 Quirks mode:
* Reads on big-endian TMS570 behave strangely differently than writes.
uint32_t *read_buf = calloc(count, sizeof(uint32_t));
/* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
uint32_t *read_ptr = read_buf;
- if (read_buf == NULL) {
+ if (!read_buf) {
LOG_ERROR("Failed to allocate read buffer");
return ERROR_FAIL;
}
/* If something failed, read TAR to find out how much data was successfully read, so we can
* at least give the caller what we have. */
if (retval != ERROR_OK) {
- uint32_t tar;
+ target_addr_t tar;
if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
/* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
- LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
+ LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT, tar);
if (nbytes > tar - address)
nbytes = tar - address;
} else {
}
int mem_ap_read_buf(struct adiv5_ap *ap,
- uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
+ uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_read(ap, buffer, size, count, address, true);
}
int mem_ap_write_buf(struct adiv5_ap *ap,
- const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
+ const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_write(ap, buffer, size, count, address, true);
}
int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
- uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
+ uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_read(ap, buffer, size, count, address, false);
}
int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
- const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
+ const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_write(ap, buffer, size, count, address, false);
}
#define DAP_POWER_DOMAIN_TIMEOUT (10)
-/* FIXME don't import ... just initialize as
- * part of DAP transport setup
-*/
-extern const struct dap_ops jtag_dp_ops;
-
/*--------------------------------------------------------------------------*/
-/**
- * Create a new DAP
- */
-struct adiv5_dap *dap_init(void)
-{
- struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
- int i;
- /* Set up with safe defaults */
- for (i = 0; i <= 255; i++) {
- dap->ap[i].dap = dap;
- dap->ap[i].ap_num = i;
- /* memaccess_tck max is 255 */
- dap->ap[i].memaccess_tck = 255;
- /* Number of bits for tar autoincrement, impl. dep. at least 10 */
- dap->ap[i].tar_autoincr_block = (1<<10);
- }
- INIT_LIST_HEAD(&dap->cmd_journal);
- return dap;
-}
-
/**
* Invalidate cached DP select and cached TAR and CSW of all APs
*/
dap->last_read = NULL;
int i;
- for (i = 0; i <= 255; i++) {
+ for (i = 0; i <= DP_APSEL_MAX; i++) {
/* force csw and tar write on the next mem-ap access */
dap->ap[i].tar_valid = false;
dap->ap[i].csw_value = 0;
{
int retval;
- LOG_DEBUG(" ");
- /* JTAG-DP or SWJ-DP, in JTAG mode
- * ... for SWD mode this is patched as part
- * of link switchover
- * FIXME: This should already be setup by the respective transport specific DAP creation.
- */
- if (!dap->ops)
- dap->ops = &jtag_dp_ops;
+ LOG_DEBUG("%s", adiv5_dap_name(dap));
+ dap->do_reconnect = false;
dap_invalidate_cache(dap);
- for (size_t i = 0; i < 30; i++) {
- /* DP initialization */
-
- retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
- if (retval == ERROR_OK)
- break;
- }
+ /*
+ * Early initialize dap->dp_ctrl_stat.
+ * In jtag mode only, if the following queue run (in dap_dp_poll_register)
+ * fails and sets the sticky error, it will trigger the clearing
+ * of the sticky. Without this initialization system and debug power
+ * would be disabled while clearing the sticky error bit.
+ */
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
+ /*
+ * This write operation clears the sticky error bit in jtag mode only and
+ * is ignored in swd mode. It also powers-up system and debug domains in
+ * both jtag and swd modes, if not done before.
+ */
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat | SSTICKYERR);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("DAP: wait CSYSPWRUPACK");
- retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
- CSYSPWRUPACK, CSYSPWRUPACK,
- DAP_POWER_DOMAIN_TIMEOUT);
- if (retval != ERROR_OK)
- return retval;
+ if (!dap->ignore_syspwrupack) {
+ LOG_DEBUG("DAP: wait CSYSPWRUPACK");
+ retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
+ CSYSPWRUPACK, CSYSPWRUPACK,
+ DAP_POWER_DOMAIN_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+ }
retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
}
+/**
+ * Initialize a DAP or do reconnect if DAP is not accessible.
+ *
+ * @param dap The DAP being initialized.
+ */
+int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
+{
+ LOG_DEBUG("%s", adiv5_dap_name(dap));
+
+ /*
+ * Early initialize dap->dp_ctrl_stat.
+ * In jtag mode only, if the following atomic reads fail and set the
+ * sticky error, it will trigger the clearing of the sticky. Without this
+ * initialization system and debug power would be disabled while clearing
+ * the sticky error bit.
+ */
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+
+ dap->do_reconnect = false;
+
+ dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
+ if (dap->do_reconnect) {
+ /* dap connect calls dap_dp_init() after transport dependent initialization */
+ return dap->ops->connect(dap);
+ } else {
+ return dap_dp_init(dap);
+ }
+}
+
/**
* Initialize a DAP. This sets up the power domains, prepares the DP
* for further use, and arranges to use AP #0 for all AP operations
int retval;
struct adiv5_dap *dap = ap->dap;
+ /* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */
+ /* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = dap_run(dap);
+ if (retval != ERROR_OK)
+ return retval;
+
+ ap->cfg_reg = cfg;
ap->tar_valid = false;
ap->csw_value = 0; /* force csw and tar write */
retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
- if (retval != ERROR_OK)
- return retval;
-
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
ap->unaligned_access_bad = dap->ti_be_32_quirks;
LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
- !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
+ !!(cfg & MEM_AP_REG_CFG_LD), !!(cfg & MEM_AP_REG_CFG_LA), !!(cfg & MEM_AP_REG_CFG_BE));
return ERROR_OK;
}
-/* CID interpretation -- see ARM IHI 0029B section 3
- * and ARM IHI 0031A table 13-3.
+/**
+ * Put the debug link into SWD mode, if the target supports it.
+ * The link's initial mode may be either JTAG (for example,
+ * with SWJ-DP after reset) or SWD.
+ *
+ * Note that targets using the JTAG-DP do not support SWD, and that
+ * some targets which could otherwise support it may have been
+ * configured to disable SWD signaling
+ *
+ * @param dap The DAP used
+ * @return ERROR_OK or else a fault code.
+ */
+int dap_to_swd(struct adiv5_dap *dap)
+{
+ LOG_DEBUG("Enter SWD mode");
+
+ return dap_send_sequence(dap, JTAG_TO_SWD);
+}
+
+/**
+ * Put the debug link into JTAG mode, if the target supports it.
+ * The link's initial mode may be either SWD or JTAG.
+ *
+ * Note that targets implemented with SW-DP do not support JTAG, and
+ * that some targets which could otherwise support it may have been
+ * configured to disable JTAG signaling
+ *
+ * @param dap The DAP used
+ * @return ERROR_OK or else a fault code.
+ */
+int dap_to_jtag(struct adiv5_dap *dap)
+{
+ LOG_DEBUG("Enter JTAG mode");
+
+ return dap_send_sequence(dap, SWD_TO_JTAG);
+}
+
+/* CID interpretation -- see ARM IHI 0029E table B2-7
+ * and ARM IHI 0031E table D1-2.
+ *
+ * From 2009/11/25 commit 21378f58b604:
+ * "OptimoDE DESS" is ARM's semicustom DSPish stuff.
+ * Let's keep it as is, for the time being
*/
static const char *class_description[16] = {
- "Reserved", "ROM table", "Reserved", "Reserved",
- "Reserved", "Reserved", "Reserved", "Reserved",
- "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
- "Reserved", "OptimoDE DESS",
- "Generic IP component", "PrimeCell or System component"
+ [0x0] = "Generic verification component",
+ [0x1] = "ROM table",
+ [0x2] = "Reserved",
+ [0x3] = "Reserved",
+ [0x4] = "Reserved",
+ [0x5] = "Reserved",
+ [0x6] = "Reserved",
+ [0x7] = "Reserved",
+ [0x8] = "Reserved",
+ [0x9] = "CoreSight component",
+ [0xA] = "Reserved",
+ [0xB] = "Peripheral Test Block",
+ [0xC] = "Reserved",
+ [0xD] = "OptimoDE DESS", /* see above */
+ [0xE] = "Generic IP component",
+ [0xF] = "CoreLink, PrimeCell or System component",
};
static bool is_dap_cid_ok(uint32_t cid)
int ap_num;
/* Maximum AP number is 255 since the SELECT register is 8 bits */
- for (ap_num = 0; ap_num <= 255; ap_num++) {
+ for (ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
/* read the IDR register of the Access Port */
uint32_t id_val = 0;
* 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
*/
- /* Reading register for a non-existant AP should not cause an error,
+ /* Reading register for a non-existent AP should not cause an error,
* but just to be sure, try to continue searching if an error does happen.
*/
if ((retval == ERROR_OK) && /* Register read success */
((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
- (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
+ (type_to_find == AP_TYPE_AHB3_AP) ? "AHB3-AP" :
+ (type_to_find == AP_TYPE_AHB5_AP) ? "AHB5-AP" :
(type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
(type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
(type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
}
LOG_DEBUG("No %s found",
- (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
+ (type_to_find == AP_TYPE_AHB3_AP) ? "AHB3-AP" :
+ (type_to_find == AP_TYPE_AHB5_AP) ? "AHB5-AP" :
(type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
(type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
(type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
}
int dap_get_debugbase(struct adiv5_ap *ap,
- uint32_t *dbgbase, uint32_t *apid)
+ target_addr_t *dbgbase, uint32_t *apid)
{
struct adiv5_dap *dap = ap->dap;
int retval;
+ uint32_t baseptr_upper, baseptr_lower;
- retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
+ if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID) {
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseptr_lower);
if (retval != ERROR_OK)
return retval;
retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
if (retval != ERROR_OK)
return retval;
+ /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
+ if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap)) {
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseptr_upper);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
+ if (!is_64bit_ap(ap))
+ baseptr_upper = 0;
+ *dbgbase = (((target_addr_t)baseptr_upper) << 32) | baseptr_lower;
+
return ERROR_OK;
}
int dap_lookup_cs_component(struct adiv5_ap *ap,
- uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
+ target_addr_t dbgbase, uint8_t type, target_addr_t *addr, int32_t *idx)
{
- uint32_t romentry, entry_offset = 0, component_base, devtype;
+ uint32_t romentry, entry_offset = 0, devtype;
+ target_addr_t component_base;
int retval;
+ dbgbase &= 0xFFFFFFFFFFFFF000ull;
*addr = 0;
do {
- retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
+ retval = mem_ap_read_atomic_u32(ap, dbgbase |
entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
- component_base = (dbgbase & 0xFFFFF000)
- + (romentry & 0xFFFFF000);
+ component_base = dbgbase + (target_addr_t)(romentry & 0xFFFFF000);
if (romentry & 0x1) {
uint32_t c_cid1;
retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
if (retval != ERROR_OK) {
- LOG_ERROR("Can't read component with base address 0x%" PRIx32
+ LOG_ERROR("Can't read component with base address " TARGET_ADDR_FMT
", the corresponding core might be turned off", component_base);
return retval;
}
return retval;
}
- retval = mem_ap_read_atomic_u32(ap,
- (component_base & 0xfffff000) | 0xfcc,
- &devtype);
+ retval = mem_ap_read_atomic_u32(ap, component_base | 0xfcc, &devtype);
if (retval != ERROR_OK)
return retval;
if ((devtype & 0xff) == type) {
}
}
entry_offset += 4;
- } while (romentry > 0);
+ } while ((romentry > 0) && (entry_offset < 0xf00));
if (!*addr)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
return ERROR_OK;
}
-static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
+static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, uint32_t *cid, uint64_t *pid)
{
assert((component_base & 0xFFF) == 0);
- assert(ap != NULL && cid != NULL && pid != NULL);
+ assert(ap && cid && pid);
uint32_t cid0, cid1, cid2, cid3;
uint32_t pid0, pid1, pid2, pid3, pid4;
{ ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
{ ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
{ ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
+ { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
+ { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
{ ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
{ ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
{ ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
{ ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
{ ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
{ ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
{ ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
{ ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
{ ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
- { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
- { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
- { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
+ { ARM_ID, 0x4e4, "Cortex-A76 ROM", "(ROM Table)", },
{ ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
{ ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
{ ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
{ ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
{ ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
{ ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
+ { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
{ ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
{ ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
{ ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
{ ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
{ ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
{ ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
+ { ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", },
{ 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
{ 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
{ 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
{ 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
{ 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
{ 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
+ { 0x1bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
+ { 0x1bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
+ { 0x1bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
+ { 0x1bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
{ 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
- { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
{ 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
+ { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
{ 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
{ 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
/* legacy comment: 0x113: what? */
{ ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
};
-static int dap_rom_display(struct command_context *cmd_ctx,
- struct adiv5_ap *ap, uint32_t dbgbase, int depth)
+static int dap_rom_display(struct command_invocation *cmd,
+ struct adiv5_ap *ap, target_addr_t dbgbase, int depth)
{
int retval;
uint64_t pid;
char tabs[16] = "";
if (depth > 16) {
- command_print(cmd_ctx, "\tTables too deep");
+ command_print(cmd, "\tTables too deep");
return ERROR_FAIL;
}
if (depth)
snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
- uint32_t base_addr = dbgbase & 0xFFFFF000;
- command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
+ target_addr_t base_addr = dbgbase & 0xFFFFFFFFFFFFF000ull;
+ command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, base_addr);
retval = dap_read_part_id(ap, base_addr, &cid, &pid);
if (retval != ERROR_OK) {
- command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
+ command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
return ERROR_OK; /* Don't abort recursion */
}
if (!is_dap_cid_ok(cid)) {
- command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
+ command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, cid);
return ERROR_OK; /* Don't abort recursion */
}
/* component may take multiple 4K pages */
uint32_t size = (pid >> 36) & 0xf;
if (size > 0)
- command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
+ command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_addr - 0x1000 * size);
- command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
+ command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
uint8_t class = (cid >> 12) & 0xf;
uint16_t part_num = pid & 0xfff;
if (designer_id & 0x80) {
/* JEP106 code */
- command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
+ command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
} else {
/* Legacy ASCII ID, clear invalid bits */
designer_id &= 0x7f;
- command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
+ command_print(cmd, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
}
break;
}
- command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
- command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
+ command_print(cmd, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
+ command_print(cmd, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
if (class == 1) { /* ROM Table */
uint32_t memtype;
return retval;
if (memtype & 0x01)
- command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
+ command_print(cmd, "\t\tMEMTYPE system memory present on bus");
else
- command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
+ command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
- command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
+ command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
tabs, entry_offset, romentry);
if (romentry & 0x01) {
- /* Recurse */
- retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
+ /* Recurse. "romentry" is signed */
+ retval = dap_rom_display(cmd, ap, base_addr + (int32_t)(romentry & 0xFFFFF000), depth + 1);
if (retval != ERROR_OK)
return retval;
} else if (romentry != 0) {
- command_print(cmd_ctx, "\t\tComponent not present");
+ command_print(cmd, "\t\tComponent not present");
} else {
- command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
+ command_print(cmd, "\t%s\tEnd of ROM table", tabs);
break;
}
}
}
break;
case 6:
- major = "Perfomance Monitor";
+ major = "Performance Monitor";
switch (minor) {
case 0:
subtype = "other";
}
break;
}
- command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
+ command_print(cmd, "\t\tType is 0x%02" PRIx8 ", %s, %s",
(uint8_t)(devtype & 0xff),
major, subtype);
/* REVISIT also show 0xfc8 DevId */
return ERROR_OK;
}
-static int dap_info_command(struct command_context *cmd_ctx,
+int dap_info_command(struct command_invocation *cmd,
struct adiv5_ap *ap)
{
int retval;
- uint32_t dbgbase, apid;
+ uint32_t apid;
+ target_addr_t dbgbase;
+ target_addr_t dbgaddr;
uint8_t mem_ap;
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
if (retval != ERROR_OK)
return retval;
- command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
+ command_print(cmd, "AP ID register 0x%8.8" PRIx32, apid);
if (apid == 0) {
- command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
+ command_print(cmd, "No AP found at this ap 0x%x", ap->ap_num);
return ERROR_FAIL;
}
switch (apid & (IDR_JEP106 | IDR_TYPE)) {
case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
- command_print(cmd_ctx, "\tType is JTAG-AP");
+ command_print(cmd, "\tType is JTAG-AP");
break;
- case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
- command_print(cmd_ctx, "\tType is MEM-AP AHB");
+ case IDR_JEP106_ARM | AP_TYPE_AHB3_AP:
+ command_print(cmd, "\tType is MEM-AP AHB3");
+ break;
+ case IDR_JEP106_ARM | AP_TYPE_AHB5_AP:
+ command_print(cmd, "\tType is MEM-AP AHB5");
break;
case IDR_JEP106_ARM | AP_TYPE_APB_AP:
- command_print(cmd_ctx, "\tType is MEM-AP APB");
+ command_print(cmd, "\tType is MEM-AP APB");
break;
case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
- command_print(cmd_ctx, "\tType is MEM-AP AXI");
+ command_print(cmd, "\tType is MEM-AP AXI");
break;
default:
- command_print(cmd_ctx, "\tUnknown AP type");
+ command_print(cmd, "\tUnknown AP type");
break;
}
*/
mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
if (mem_ap) {
- command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
+ if (is_64bit_ap(ap))
+ dbgaddr = 0xFFFFFFFFFFFFFFFFull;
+ else
+ dbgaddr = 0xFFFFFFFFul;
- if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
- command_print(cmd_ctx, "\tNo ROM table present");
+ command_print(cmd, "MEM-AP BASE " TARGET_ADDR_FMT, dbgbase);
+
+ if (dbgbase == dbgaddr || (dbgbase & 0x3) == 0x2) {
+ command_print(cmd, "\tNo ROM table present");
} else {
if (dbgbase & 0x01)
- command_print(cmd_ctx, "\tValid ROM table present");
+ command_print(cmd, "\tValid ROM table present");
else
- command_print(cmd_ctx, "\tROM table in legacy format");
+ command_print(cmd, "\tROM table in legacy format");
- dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
+ dap_rom_display(cmd, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, 0);
}
}
return ERROR_OK;
}
-int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
+enum adiv5_cfg_param {
+ CFG_DAP,
+ CFG_AP_NUM,
+ CFG_BASEADDR,
+ CFG_CTIBASE, /* DEPRECATED */
+};
+
+static const struct jim_nvp nvp_config_opts[] = {
+ { .name = "-dap", .value = CFG_DAP },
+ { .name = "-ap-num", .value = CFG_AP_NUM },
+ { .name = "-baseaddr", .value = CFG_BASEADDR },
+ { .name = "-ctibase", .value = CFG_CTIBASE }, /* DEPRECATED */
+ { .name = NULL, .value = -1 }
+};
+
+static int adiv5_jim_spot_configure(struct jim_getopt_info *goi,
+ struct adiv5_dap **dap_p, int *ap_num_p, uint32_t *base_p)
{
- struct adiv5_private_config *pc;
- const char *arg;
- jim_wide ap_num;
- int e;
+ if (!goi->argc)
+ return JIM_OK;
- /* check if argv[0] is for us */
- arg = Jim_GetString(goi->argv[0], NULL);
- if (strcmp(arg, "-ap-num"))
- return JIM_CONTINUE;
+ Jim_SetEmptyResult(goi->interp);
- e = Jim_GetOpt_String(goi, &arg, NULL);
+ struct jim_nvp *n;
+ int e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts,
+ goi->argv[0], &n);
if (e != JIM_OK)
- return e;
+ return JIM_CONTINUE;
- if (goi->argc == 0) {
- Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-ap-num ?ap-number? ...");
- return JIM_ERR;
- }
+ /* base_p can be NULL, then '-baseaddr' option is treated as unknown */
+ if (!base_p && (n->value == CFG_BASEADDR || n->value == CFG_CTIBASE))
+ return JIM_CONTINUE;
- e = Jim_GetOpt_Wide(goi, &ap_num);
+ e = jim_getopt_obj(goi, NULL);
if (e != JIM_OK)
return e;
- if (target->private_config == NULL) {
+ switch (n->value) {
+ case CFG_DAP:
+ if (goi->isconfigure) {
+ Jim_Obj *o_t;
+ struct adiv5_dap *dap;
+ e = jim_getopt_obj(goi, &o_t);
+ if (e != JIM_OK)
+ return e;
+ dap = dap_instance_by_jim_obj(goi->interp, o_t);
+ if (!dap) {
+ Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
+ return JIM_ERR;
+ }
+ if (*dap_p && *dap_p != dap) {
+ Jim_SetResultString(goi->interp,
+ "DAP assignment cannot be changed!", -1);
+ return JIM_ERR;
+ }
+ *dap_p = dap;
+ } else {
+ if (goi->argc)
+ goto err_no_param;
+ if (!*dap_p) {
+ Jim_SetResultString(goi->interp, "DAP not configured", -1);
+ return JIM_ERR;
+ }
+ Jim_SetResultString(goi->interp, adiv5_dap_name(*dap_p), -1);
+ }
+ break;
+
+ case CFG_AP_NUM:
+ if (goi->isconfigure) {
+ jim_wide ap_num;
+ e = jim_getopt_wide(goi, &ap_num);
+ if (e != JIM_OK)
+ return e;
+ if (ap_num < 0 || ap_num > DP_APSEL_MAX) {
+ Jim_SetResultString(goi->interp, "Invalid AP number!", -1);
+ return JIM_ERR;
+ }
+ *ap_num_p = ap_num;
+ } else {
+ if (goi->argc)
+ goto err_no_param;
+ if (*ap_num_p == DP_APSEL_INVALID) {
+ Jim_SetResultString(goi->interp, "AP number not configured", -1);
+ return JIM_ERR;
+ }
+ Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *ap_num_p));
+ }
+ break;
+
+ case CFG_CTIBASE:
+ LOG_WARNING("DEPRECATED! use \'-baseaddr' not \'-ctibase\'");
+ /* fall through */
+ case CFG_BASEADDR:
+ if (goi->isconfigure) {
+ jim_wide base;
+ e = jim_getopt_wide(goi, &base);
+ if (e != JIM_OK)
+ return e;
+ *base_p = (uint32_t)base;
+ } else {
+ if (goi->argc)
+ goto err_no_param;
+ Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *base_p));
+ }
+ break;
+ };
+
+ return JIM_OK;
+
+err_no_param:
+ Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "NO PARAMS");
+ return JIM_ERR;
+}
+
+int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
+{
+ struct adiv5_private_config *pc;
+ int e;
+
+ pc = (struct adiv5_private_config *)target->private_config;
+ if (!pc) {
pc = calloc(1, sizeof(struct adiv5_private_config));
+ pc->ap_num = DP_APSEL_INVALID;
target->private_config = pc;
- pc->ap_num = ap_num;
}
+ target->has_dap = true;
+
+ e = adiv5_jim_spot_configure(goi, &pc->dap, &pc->ap_num, NULL);
+ if (e != JIM_OK)
+ return e;
+
+ if (pc->dap && !target->dap_configured) {
+ if (target->tap_configured) {
+ pc->dap = NULL;
+ Jim_SetResultString(goi->interp,
+ "-chain-position and -dap configparams are mutually exclusive!", -1);
+ return JIM_ERR;
+ }
+ target->tap = pc->dap->tap;
+ target->dap_configured = true;
+ }
return JIM_OK;
}
+int adiv5_verify_config(struct adiv5_private_config *pc)
+{
+ if (!pc)
+ return ERROR_FAIL;
+
+ if (!pc->dap)
+ return ERROR_FAIL;
+
+ return ERROR_OK;
+}
+
+int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg,
+ struct jim_getopt_info *goi)
+{
+ return adiv5_jim_spot_configure(goi, &cfg->dap, &cfg->ap_num, &cfg->base);
+}
+
+int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p)
+{
+ p->dap = NULL;
+ p->ap_num = DP_APSEL_INVALID;
+ p->base = 0;
+ return ERROR_OK;
+}
+
COMMAND_HANDLER(handle_dap_info_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
uint32_t apsel;
switch (CMD_ARGC) {
break;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
- if (apsel >= 256)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (apsel > DP_APSEL_MAX) {
+ command_print(CMD, "Invalid AP number");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
}
- return dap_info_command(CMD_CTX, &dap->ap[apsel]);
+ return dap_info_command(CMD, &dap->ap[apsel]);
}
COMMAND_HANDLER(dap_baseaddr_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
- uint32_t apsel, baseaddr;
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
+ uint32_t apsel, baseaddr_lower, baseaddr_upper;
+ struct adiv5_ap *ap;
+ target_addr_t baseaddr;
int retval;
+ baseaddr_upper = 0;
+
switch (CMD_ARGC) {
case 0:
apsel = dap->apsel;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel >= 256)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (apsel > DP_APSEL_MAX) {
+ command_print(CMD, "Invalid AP number");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
* though they're not common for now. This should
* use the ID register to verify it's a MEM-AP.
*/
- retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
- if (retval != ERROR_OK)
- return retval;
- retval = dap_run(dap);
+
+ ap = dap_ap(dap, apsel);
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseaddr_lower);
+
+ if (retval == ERROR_OK && ap->cfg_reg == MEM_AP_REG_CFG_INVALID)
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
+
+ if (retval == ERROR_OK && (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap))) {
+ /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseaddr_upper);
+ }
+
+ if (retval == ERROR_OK)
+ retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
- command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
+ if (is_64bit_ap(ap)) {
+ baseaddr = (((target_addr_t)baseaddr_upper) << 32) | baseaddr_lower;
+ command_print(CMD, "0x%016" PRIx64, baseaddr);
+ } else
+ command_print(CMD, "0x%08" PRIx32, baseaddr_lower);
- return retval;
+ return ERROR_OK;
}
COMMAND_HANDLER(dap_memaccess_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
uint32_t memaccess_tck;
switch (CMD_ARGC) {
}
dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
- command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
+ command_print(CMD, "memory bus access delay set to %" PRIu32 " tck",
dap->ap[dap->apsel].memaccess_tck);
return ERROR_OK;
COMMAND_HANDLER(dap_apsel_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
- uint32_t apsel, apid;
- int retval;
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
+ uint32_t apsel;
switch (CMD_ARGC) {
case 0:
- apsel = dap->apsel;
- break;
+ command_print(CMD, "%" PRIu32, dap->apsel);
+ return ERROR_OK;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel >= 256)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (apsel > DP_APSEL_MAX) {
+ command_print(CMD, "Invalid AP number");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
}
dap->apsel = apsel;
-
- retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
- if (retval != ERROR_OK)
- return retval;
- retval = dap_run(dap);
- if (retval != ERROR_OK)
- return retval;
-
- command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
- apsel, apid);
-
- return retval;
+ return ERROR_OK;
}
COMMAND_HANDLER(dap_apcsw_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
- uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
+ uint32_t apcsw = dap->ap[dap->apsel].csw_default;
+ uint32_t csw_val, csw_mask;
switch (CMD_ARGC) {
case 0:
- command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
- (dap->apsel), apcsw);
- break;
+ command_print(CMD, "ap %" PRIu32 " selected, csw 0x%8.8" PRIx32,
+ dap->apsel, apcsw);
+ return ERROR_OK;
case 1:
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
- /* AP address is in bits 31:24 of DP_SELECT */
- if (sprot > 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
- if (sprot)
- apcsw |= CSW_SPROT;
+ if (strcmp(CMD_ARGV[0], "default") == 0)
+ csw_val = CSW_AHB_DEFAULT;
else
- apcsw &= ~CSW_SPROT;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
+
+ if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
+ LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
+ apcsw = csw_val;
+ break;
+ case 2:
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
+ if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
+ LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
+ apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_HANDLER(dap_apid_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
uint32_t apsel, apid;
int retval;
case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel >= 256)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (apsel > DP_APSEL_MAX) {
+ command_print(CMD, "Invalid AP number");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
if (retval != ERROR_OK)
return retval;
- command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
+ command_print(CMD, "0x%8.8" PRIx32, apid);
return retval;
}
COMMAND_HANDLER(dap_apreg_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
uint32_t apsel, reg, value;
+ struct adiv5_ap *ap;
int retval;
if (CMD_ARGC < 2 || CMD_ARGC > 3)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel >= 256)
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (apsel > DP_APSEL_MAX) {
+ command_print(CMD, "Invalid AP number");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
+
+ ap = dap_ap(dap, apsel);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
- if (reg >= 256 || (reg & 3))
- return ERROR_COMMAND_SYNTAX_ERROR;
+ if (reg >= 256 || (reg & 3)) {
+ command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
if (CMD_ARGC == 3) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
- retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
+ switch (reg) {
+ case MEM_AP_REG_CSW:
+ ap->csw_value = 0; /* invalid, in case write fails */
+ retval = dap_queue_ap_write(ap, reg, value);
+ if (retval == ERROR_OK)
+ ap->csw_value = value;
+ break;
+ case MEM_AP_REG_TAR:
+ retval = dap_queue_ap_write(ap, reg, value);
+ if (retval == ERROR_OK)
+ ap->tar_value = (ap->tar_value & ~0xFFFFFFFFull) | value;
+ else {
+ /* To track independent writes to TAR and TAR64, two tar_valid flags */
+ /* should be used. To keep it simple, tar_valid is only invalidated on a */
+ /* write fail. This approach causes a later re-write of the TAR and TAR64 */
+ /* if tar_valid is false. */
+ ap->tar_valid = false;
+ }
+ break;
+ case MEM_AP_REG_TAR64:
+ retval = dap_queue_ap_write(ap, reg, value);
+ if (retval == ERROR_OK)
+ ap->tar_value = (ap->tar_value & 0xFFFFFFFFull) | (((target_addr_t)value) << 32);
+ else {
+ /* See above comment for the MEM_AP_REG_TAR failed write case */
+ ap->tar_valid = false;
+ }
+ break;
+ default:
+ retval = dap_queue_ap_write(ap, reg, value);
+ break;
+ }
} else {
- retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
+ retval = dap_queue_ap_read(ap, reg, &value);
}
if (retval == ERROR_OK)
retval = dap_run(dap);
return retval;
if (CMD_ARGC == 2)
- command_print(CMD_CTX, "0x%08" PRIx32, value);
+ command_print(CMD, "0x%08" PRIx32, value);
return retval;
}
-COMMAND_HANDLER(dap_ti_be_32_quirks_command)
+COMMAND_HANDLER(dap_dpreg_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target_to_arm(target);
- struct adiv5_dap *dap = arm->dap;
-
- uint32_t enable = dap->ti_be_32_quirks;
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
+ uint32_t reg, value;
+ int retval;
- switch (CMD_ARGC) {
- case 0:
- break;
- case 1:
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
- if (enable > 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
- break;
- default:
+ if (CMD_ARGC < 1 || CMD_ARGC > 2)
return ERROR_COMMAND_SYNTAX_ERROR;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg);
+ if (reg >= 256 || (reg & 3)) {
+ command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
- dap->ti_be_32_quirks = enable;
- command_print(CMD_CTX, "TI BE-32 quirks mode %s",
- enable ? "enabled" : "disabled");
- return 0;
+ if (CMD_ARGC == 2) {
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
+ retval = dap_queue_dp_write(dap, reg, value);
+ } else {
+ retval = dap_queue_dp_read(dap, reg, &value);
+ }
+ if (retval == ERROR_OK)
+ retval = dap_run(dap);
+
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (CMD_ARGC == 1)
+ command_print(CMD, "0x%08" PRIx32, value);
+
+ return retval;
}
-static const struct command_registration dap_commands[] = {
+COMMAND_HANDLER(dap_ti_be_32_quirks_command)
+{
+ struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
+ return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->ti_be_32_quirks,
+ "TI BE-32 quirks mode");
+}
+
+const struct command_registration dap_instance_commands[] = {
{
.name = "info",
.handler = handle_dap_info_command,
{
.name = "apsel",
.handler = dap_apsel_command,
- .mode = COMMAND_EXEC,
+ .mode = COMMAND_ANY,
.help = "Set the currently selected AP (default 0) "
"and display the result",
.usage = "[ap_num]",
{
.name = "apcsw",
.handler = dap_apcsw_command,
- .mode = COMMAND_EXEC,
- .help = "Set csw access bit ",
- .usage = "[sprot]",
+ .mode = COMMAND_ANY,
+ .help = "Set CSW default bits",
+ .usage = "[value [mask]]",
},
{
"(reg is byte address of a word register, like 0 4 8...)",
.usage = "ap_num reg [value]",
},
+ {
+ .name = "dpreg",
+ .handler = dap_dpreg_command,
+ .mode = COMMAND_EXEC,
+ .help = "read/write a register from DP "
+ "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
+ .usage = "reg [value]",
+ },
{
.name = "baseaddr",
.handler = dap_baseaddr_command,
},
COMMAND_REGISTRATION_DONE
};
-
-const struct command_registration dap_command_handlers[] = {
- {
- .name = "dap",
- .mode = COMMAND_EXEC,
- .help = "DAP command group",
- .usage = "",
- .chain = dap_commands,
- },
- COMMAND_REGISTRATION_DONE
-};
Code Review / openocd.git / blobdiff