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arm_adi_v5: update coresight class names
[openocd.git] / src / target / arm_adi_v5.c
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index c458ffd46c83756c72dfd8105ea2c31ec18c6bad..65a8bc4c7c55d6cd71454615b7812c4a83f1a276 100644 (file)
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -648,7 +648,7 @@ void dap_invalidate_cache(struct adiv5_dap *dap)
        dap->last_read = NULL;
 
        int i;
-       for (i = 0; i <= 255; i++) {
+       for (i = 0; i <= DP_APSEL_MAX; i++) {
                /* force csw and tar write on the next mem-ap access */
                dap->ap[i].tar_valid = false;
                dap->ap[i].csw_value = 0;
@@ -865,15 +865,30 @@ int dap_to_jtag(struct adiv5_dap *dap)
        return dap_send_sequence(dap, SWD_TO_JTAG);
 }
 
-/* CID interpretation -- see ARM IHI 0029B section 3
- * and ARM IHI 0031A table 13-3.
+/* CID interpretation -- see ARM IHI 0029E table B2-7
+ * and ARM IHI 0031E table D1-2.
+ *
+ * From 2009/11/25 commit 21378f58b604:
+ *   "OptimoDE DESS" is ARM's semicustom DSPish stuff.
+ * Let's keep it as is, for the time being
  */
 static const char *class_description[16] = {
-       "Reserved", "ROM table", "Reserved", "Reserved",
-       "Reserved", "Reserved", "Reserved", "Reserved",
-       "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
-       "Reserved", "OptimoDE DESS",
-       "Generic IP component", "PrimeCell or System component"
+       [0x0] = "Generic verification component",
+       [0x1] = "ROM table",
+       [0x2] = "Reserved",
+       [0x3] = "Reserved",
+       [0x4] = "Reserved",
+       [0x5] = "Reserved",
+       [0x6] = "Reserved",
+       [0x7] = "Reserved",
+       [0x8] = "Reserved",
+       [0x9] = "CoreSight component",
+       [0xA] = "Reserved",
+       [0xB] = "Peripheral Test Block",
+       [0xC] = "Reserved",
+       [0xD] = "OptimoDE DESS", /* see above */
+       [0xE] = "Generic IP component",
+       [0xF] = "CoreLink, PrimeCell or System component",
 };
 
 static bool is_dap_cid_ok(uint32_t cid)
@@ -946,25 +961,30 @@ int dap_get_debugbase(struct adiv5_ap *ap,
        int retval;
        uint32_t baseptr_upper, baseptr_lower;
 
-       baseptr_upper = 0;
-
-       if (is_64bit_ap(ap)) {
-               /* Read higher order 32-bits of base address */
-               retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseptr_upper);
+       if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID) {
+               retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
                if (retval != ERROR_OK)
                        return retval;
        }
-
        retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseptr_lower);
        if (retval != ERROR_OK)
                return retval;
        retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
        if (retval != ERROR_OK)
                return retval;
+       /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
+       if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap)) {
+               retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseptr_upper);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
+
        retval = dap_run(dap);
        if (retval != ERROR_OK)
                return retval;
 
+       if (!is_64bit_ap(ap))
+               baseptr_upper = 0;
        *dbgbase = (((target_addr_t)baseptr_upper) << 32) | baseptr_lower;
 
        return ERROR_OK;
@@ -1028,7 +1048,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap,
 static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, uint32_t *cid, uint64_t *pid)
 {
        assert((component_base & 0xFFF) == 0);
-       assert(ap != NULL && cid != NULL && pid != NULL);
+       assert(ap && cid && pid);
 
        uint32_t cid0, cid1, cid2, cid3;
        uint32_t pid0, pid1, pid2, pid3, pid4;
@@ -1138,6 +1158,7 @@ static const struct {
        { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM",          "(Private Peripheral Bus ROM Table)", },
        { ARM_ID, 0x4c8, "Cortex-M7 ROM",              "(ROM Table)", },
        { ARM_ID, 0x4e0, "Cortex-A35 ROM",             "(v7 Memory Map ROM Table)", },
+       { ARM_ID, 0x4e4, "Cortex-A76 ROM",             "(ROM Table)", },
        { ARM_ID, 0x906, "CoreSight CTI",              "(Cross Trigger)", },
        { ARM_ID, 0x907, "CoreSight ETB",              "(Trace Buffer)", },
        { ARM_ID, 0x908, "CoreSight CSTF",             "(Trace Funnel)", },
@@ -1194,6 +1215,7 @@ static const struct {
        { ARM_ID, 0xd04, "Cortex-A35 Debug",           "(Debug Unit)", },
        { ARM_ID, 0xd07, "Cortex-A57 Debug",           "(Debug Unit)", },
        { ARM_ID, 0xd08, "Cortex-A72 Debug",           "(Debug Unit)", },
+       { ARM_ID, 0xd0b, "Cortex-A76 Debug",           "(Debug Unit)", },
        { 0x097,  0x9af, "MSP432 ROM",                 "(ROM Table)" },
        { 0x09f,  0xcd0, "Atmel CPU with DSU",         "(CPU)" },
        { 0x0c1,  0x1db, "XMC4500 ROM",                "(ROM Table)" },
@@ -1201,6 +1223,10 @@ static const struct {
        { 0x0c1,  0x1ed, "XMC1000 ROM",                "(ROM Table)" },
        { 0x0E5,  0x000, "SHARC+/Blackfin+",           "", },
        { 0x0F0,  0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
+       { 0x1bf,  0x100, "Brahma-B53 Debug",           "(Debug Unit)", },
+       { 0x1bf,  0x9d3, "Brahma-B53 PMU",             "(Performance Monitor Unit)", },
+       { 0x1bf,  0x4a1, "Brahma-B53 ROM",             "(ROM Table)", },
+       { 0x1bf,  0x721, "Brahma-B53 ROM",             "(ROM Table)", },
        { 0x3eb,  0x181, "Tegra 186 ROM",              "(ROM Table)", },
        { 0x3eb,  0x202, "Denver ETM",                 "(Denver Embedded Trace)", },
        { 0x3eb,  0x211, "Tegra 210 ROM",              "(ROM Table)", },
@@ -1304,8 +1330,8 @@ static int dap_rom_display(struct command_invocation *cmd,
                        command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
                                        tabs, entry_offset, romentry);
                        if (romentry & 0x01) {
-                               /* Recurse */
-                               retval = dap_rom_display(cmd, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
+                               /* Recurse. "romentry" is signed */
+                               retval = dap_rom_display(cmd, ap, base_addr + (int32_t)(romentry & 0xFFFFF000), depth + 1);
                                if (retval != ERROR_OK)
                                        return retval;
                        } else if (romentry != 0) {
@@ -1762,20 +1788,26 @@ COMMAND_HANDLER(dap_baseaddr_command)
        ap = dap_ap(dap, apsel);
        retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseaddr_lower);
 
-       if (is_64bit_ap(ap) && retval == ERROR_OK)
+       if (retval == ERROR_OK && ap->cfg_reg == MEM_AP_REG_CFG_INVALID)
+               retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
+
+       if (retval == ERROR_OK && (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap))) {
+               /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
                retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseaddr_upper);
+       }
+
+       if (retval == ERROR_OK)
+               retval = dap_run(dap);
        if (retval != ERROR_OK)
                return retval;
-       retval = dap_run(dap);
-       if (retval != ERROR_OK)
-               return retval;
+
        if (is_64bit_ap(ap)) {
                baseaddr = (((target_addr_t)baseaddr_upper) << 32) | baseaddr_lower;
                command_print(CMD, "0x%016" PRIx64, baseaddr);
        } else
                command_print(CMD, "0x%08" PRIx32, baseaddr_lower);
 
-       return retval;
+       return ERROR_OK;
 }
 
 COMMAND_HANDLER(dap_memaccess_command)
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