for (writecount = 0; writecount < blocksize; writecount++)
{
retval = dap_queue_ap_write(dap, AP_REG_DRW,
- *(uint32_t *) (buffer + 4 * writecount));
+ *(uint32_t *) ((void *) (buffer + 4 * writecount)));
if (retval != ERROR_OK)
break;
}
- if (dap_run(dap) == ERROR_OK)
+ if ((retval = dap_run(dap)) == ERROR_OK)
{
wcount = wcount - blocksize;
address = address + 4 * blocksize;
if (errorcount > 1)
{
LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
- /* REVISIT return the *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
}
if (nbytes < 4)
{
- if (mem_ap_write_buf_u16(dap, buffer,
- nbytes, address) != ERROR_OK)
+ retval = mem_ap_write_buf_u16(dap, buffer,
+ nbytes, address);
+ if (retval != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
address, count);
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
address += nbytes >> 1;
if (retval != ERROR_OK)
break;
- if (dap_run(dap) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
address, count);
- /* REVISIT return *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
}
if (nbytes < 4)
{
- if (mem_ap_write_buf_u8(dap, buffer, nbytes, address) != ERROR_OK)
+ retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
+ if (retval != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
address, count);
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
address += nbytes;
if (retval != ERROR_OK)
break;
- if (dap_run(dap) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
address, count);
- /* REVISIT return *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
}
do
{
retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
- if (dap_run(dap) != ERROR_OK)
+ if (retval != ERROR_OK)
+ return retval;
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
- /* REVISIT return the *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
nbytes = MIN((readcount << 1), 4);
do
{
retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
- if (dap_run(dap) != ERROR_OK)
+ if (retval != ERROR_OK)
+ return retval;
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
- /* REVISIT return the *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
nbytes = MIN(readcount, 4);
*/
int ahbap_debugport_init(struct adiv5_dap *dap)
{
- uint32_t idreg, romaddr, dummy;
+ uint32_t dummy;
uint32_t ctrlstat;
int cnt = 0;
int retval;
if (retval != ERROR_OK)
return retval;
- /*
- * REVISIT this isn't actually *initializing* anything in an AP,
- * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
- * Should it? If the ROM address is valid, is this the right
- * place to scan the table and do any topology detection?
- */
- retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
- retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
-
- if ((retval = dap_run(dap)) != ERROR_OK)
- return retval;
-
- LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32
- ", Debug ROM Address 0x%" PRIx32,
- dap->apsel, idreg, romaddr);
-
return ERROR_OK;
}
&& ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
}
-static int dap_info_command(struct command_context *cmd_ctx,
- struct adiv5_dap *dap, int apsel)
+struct broken_cpu {
+ uint32_t dbgbase;
+ uint32_t apid;
+ uint32_t correct_dbgbase;
+ char *model;
+} broken_cpus[] = {
+ { 0x80000000, 0x04770002, 0x60000000, "imx51" },
+};
+
+int dap_get_debugbase(struct adiv5_dap *dap, int apsel,
+ uint32_t *out_dbgbase, uint32_t *out_apid)
{
+ uint32_t apselold;
int retval;
+ unsigned int i;
uint32_t dbgbase, apid;
- int romtable_present = 0;
- uint8_t mem_ap;
- uint32_t apselold;
/* AP address is in bits 31:24 of DP_SELECT */
if (apsel >= 256)
apselold = dap->apsel;
dap_ap_select(dap, apsel);
+
retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
+ /* Some CPUs are messed up, so fixup if needed. */
+ for (i = 0; i < sizeof(broken_cpus)/sizeof(struct broken_cpu); i++)
+ if (broken_cpus[i].dbgbase == dbgbase &&
+ broken_cpus[i].apid == apid) {
+ LOG_WARNING("Found broken CPU (%s), trying to fixup "
+ "ROM Table location from 0x%08x to 0x%08x",
+ broken_cpus[i].model, dbgbase,
+ broken_cpus[i].correct_dbgbase);
+ dbgbase = broken_cpus[i].correct_dbgbase;
+ break;
+ }
+
+ dap_ap_select(dap, apselold);
+
+ /* The asignment happens only here to prevent modification of these
+ * values before they are certain. */
+ *out_dbgbase = dbgbase;
+ *out_apid = apid;
+
+ return ERROR_OK;
+}
+
+int dap_lookup_cs_component(struct adiv5_dap *dap, int apsel,
+ uint32_t dbgbase, uint8_t type, uint32_t *addr)
+{
+ uint32_t apselold;
+ uint32_t romentry, entry_offset = 0, component_base, devtype;
+ int retval = ERROR_FAIL;
+
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
+
+ apselold = dap->apsel;
+ dap_ap_select(dap, apsel);
+
+ do
+ {
+ retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
+ entry_offset, &romentry);
+ if (retval != ERROR_OK)
+ return retval;
+
+ component_base = (dbgbase & 0xFFFFF000)
+ + (romentry & 0xFFFFF000);
+
+ if (romentry & 0x1) {
+ retval = mem_ap_read_atomic_u32(dap,
+ (component_base & 0xfffff000) | 0xfcc,
+ &devtype);
+ if ((devtype & 0xff) == type) {
+ *addr = component_base;
+ retval = ERROR_OK;
+ break;
+ }
+ }
+ entry_offset += 4;
+ } while (romentry > 0);
+
+ dap_ap_select(dap, apselold);
+
+ return retval;
+}
+
+static int dap_info_command(struct command_context *cmd_ctx,
+ struct adiv5_dap *dap, int apsel)
+{
+ int retval;
+ uint32_t dbgbase, apid;
+ int romtable_present = 0;
+ uint8_t mem_ap;
+ uint32_t apselold;
+
+ retval = dap_get_debugbase(dap, apsel, &dbgbase, &apid);
+ if (retval != ERROR_OK)
+ return retval;
+
+ apselold = dap->apsel;
+ dap_ap_select(dap, apsel);
+
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
command_print(cmd_ctx, "\tROM table in legacy format");
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
entry_offset = 0;
do
{
- mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
+ retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
+ if (retval != ERROR_OK)
+ return retval;
command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
if (romentry&0x01)
{
/* IDs are in last 4K section */
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFE0, &c_pid0);
+ if (retval != ERROR_OK)
+ return retval;
c_pid0 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFE4, &c_pid1);
+ if (retval != ERROR_OK)
+ return retval;
c_pid1 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFE8, &c_pid2);
+ if (retval != ERROR_OK)
+ return retval;
c_pid2 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFEC, &c_pid3);
+ if (retval != ERROR_OK)
+ return retval;
c_pid3 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFD0, &c_pid4);
+ if (retval != ERROR_OK)
+ return retval;
c_pid4 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFF0, &c_cid0);
+ if (retval != ERROR_OK)
+ return retval;
c_cid0 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFF4, &c_cid1);
+ if (retval != ERROR_OK)
+ return retval;
c_cid1 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFF8, &c_cid2);
+ if (retval != ERROR_OK)
+ return retval;
c_cid2 &= 0xff;
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
component_base + 0xFFC, &c_cid3);
+ if (retval != ERROR_OK)
+ return retval;
c_cid3 &= 0xff;
unsigned minor;
char *major = "Reserved", *subtype = "Reserved";
- mem_ap_read_atomic_u32(dap,
+ retval = mem_ap_read_atomic_u32(dap,
(component_base & 0xfffff000) | 0xfcc,
&devtype);
+ if (retval != ERROR_OK)
+ return retval;
minor = (devtype >> 4) & 0x0f;
switch (devtype & 0x0f) {
case 0:
* use the ID register to verify it's a MEM-AP.
*/
retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
dap_ap_select(dap, apsel);
retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
dap_ap_select(dap, apsel);
retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;