+COMMAND_HANDLER(handle_dap_info_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm *arm = target_to_arm(target);
+ struct adiv5_dap *dap = arm->dap;
+ uint32_t apsel;
+
+ switch (CMD_ARGC) {
+ case 0:
+ apsel = dap->apsel;
+ break;
+ case 1:
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ return dap_info_command(CMD_CTX, dap, apsel);
+}
+
+COMMAND_HANDLER(dap_baseaddr_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm *arm = target_to_arm(target);
+ struct adiv5_dap *dap = arm->dap;
+
+ uint32_t apsel, apselsave, baseaddr;
+ int retval;
+
+ apselsave = dap->apsel;
+ switch (CMD_ARGC) {
+ case 0:
+ apsel = dap->apsel;
+ break;
+ case 1:
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ if (apselsave != apsel)
+ dap_ap_select(dap, apsel);
+
+ /* NOTE: assumes we're talking to a MEM-AP, which
+ * has a base address. There are other kinds of AP,
+ * though they're not common for now. This should
+ * use the ID register to verify it's a MEM-AP.
+ */
+ retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
+ retval = dap_run(dap);
+ if (retval != ERROR_OK)
+ return retval;
+
+ command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
+
+ if (apselsave != apsel)
+ dap_ap_select(dap, apselsave);
+
+ return retval;
+}
+
+COMMAND_HANDLER(dap_memaccess_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm *arm = target_to_arm(target);
+ struct adiv5_dap *dap = arm->dap;
+
+ uint32_t memaccess_tck;
+
+ switch (CMD_ARGC) {
+ case 0:
+ memaccess_tck = dap->memaccess_tck;
+ break;
+ case 1:
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ dap->memaccess_tck = memaccess_tck;
+
+ command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
+ dap->memaccess_tck);
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(dap_apsel_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm *arm = target_to_arm(target);
+ struct adiv5_dap *dap = arm->dap;
+
+ uint32_t apsel, apid;
+ int retval;
+
+ switch (CMD_ARGC) {
+ case 0:
+ apsel = 0;
+ break;
+ case 1:
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ dap_ap_select(dap, apsel);
+ retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ retval = dap_run(dap);
+ if (retval != ERROR_OK)
+ return retval;
+
+ command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
+ apsel, apid);
+
+ return retval;
+}
+
+COMMAND_HANDLER(dap_apid_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm *arm = target_to_arm(target);
+ struct adiv5_dap *dap = arm->dap;
+
+ uint32_t apsel, apselsave, apid;
+ int retval;
+
+ apselsave = dap->apsel;
+ switch (CMD_ARGC) {
+ case 0:
+ apsel = dap->apsel;
+ break;
+ case 1:
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+ /* AP address is in bits 31:24 of DP_SELECT */
+ if (apsel >= 256)
+ return ERROR_INVALID_ARGUMENTS;
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ if (apselsave != apsel)
+ dap_ap_select(dap, apsel);
+
+ retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ retval = dap_run(dap);
+ if (retval != ERROR_OK)
+ return retval;
+
+ command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
+ if (apselsave != apsel)
+ dap_ap_select(dap, apselsave);
+
+ return retval;
+}
+
+static const struct command_registration dap_commands[] = {
+ {
+ .name = "info",
+ .handler = handle_dap_info_command,
+ .mode = COMMAND_EXEC,
+ .help = "display ROM table for MEM-AP "
+ "(default currently selected AP)",
+ .usage = "[ap_num]",
+ },
+ {
+ .name = "apsel",
+ .handler = dap_apsel_command,
+ .mode = COMMAND_EXEC,
+ .help = "Set the currently selected AP (default 0) "
+ "and display the result",
+ .usage = "[ap_num]",
+ },
+ {
+ .name = "apid",
+ .handler = dap_apid_command,
+ .mode = COMMAND_EXEC,
+ .help = "return ID register from AP "
+ "(default currently selected AP)",
+ .usage = "[ap_num]",
+ },
+ {
+ .name = "baseaddr",
+ .handler = dap_baseaddr_command,
+ .mode = COMMAND_EXEC,
+ .help = "return debug base address from MEM-AP "
+ "(default currently selected AP)",
+ .usage = "[ap_num]",
+ },
+ {
+ .name = "memaccess",
+ .handler = dap_memaccess_command,
+ .mode = COMMAND_EXEC,
+ .help = "set/get number of extra tck for MEM-AP memory "
+ "bus access [0-255]",
+ .usage = "[cycles]",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+const struct command_registration dap_command_handlers[] = {
+ {
+ .name = "dap",
+ .mode = COMMAND_EXEC,
+ .help = "DAP command group",
+ .chain = dap_commands,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+
+/*
+ * This represents the bits which must be sent out on TMS/SWDIO to
+ * switch a DAP implemented using an SWJ-DP module into SWD mode.
+ * These bits are stored (and transmitted) LSB-first.
+ *
+ * See the DAP-Lite specification, section 2.2.5 for information
+ * about making the debug link select SWD or JTAG. (Similar info
+ * is in a few other ARM documents.)
+ */
+static const uint8_t jtag2swd_bitseq[] = {
+ /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
+ * putting both JTAG and SWD logic into reset state.
+ */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ /* Switching sequence enables SWD and disables JTAG
+ * NOTE: bits in the DP's IDCODE may expose the need for
+ * an old/deprecated sequence (0xb6 0xed).
+ */
+ 0x9e, 0xe7,
+ /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
+ * putting both JTAG and SWD logic into reset state.
+ */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+
+/**
+ * Put the debug link into SWD mode, if the target supports it.
+ * The link's initial mode may be either JTAG (for example,
+ * with SWJ-DP after reset) or SWD.
+ *
+ * @param target Enters SWD mode (if possible).
+ *
+ * Note that targets using the JTAG-DP do not support SWD, and that
+ * some targets which could otherwise support it may have have been
+ * configured to disable SWD signaling
+ *
+ * @return ERROR_OK or else a fault code.
+ */
+int dap_to_swd(struct target *target)
+{
+ int retval;
+
+ LOG_DEBUG("Enter SWD mode");
+
+ /* REVISIT it's nasty to need to make calls to a "jtag"
+ * subsystem if the link isn't in JTAG mode...
+ */
+
+ retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
+ jtag2swd_bitseq, TAP_INVALID);
+ if (retval == ERROR_OK)
+ retval = jtag_execute_queue();
+
+ /* REVISIT set up the DAP's ops vector for SWD mode. */
+
+ return retval;
+}
+