ADIv5 DAP ops switching to JTAG or SWD modes

[openocd.git] / src / target / arm_adi_v5.h

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 759f2333a6fde8110824d6e0ebfce238ee0e32c5..5c5ca4f041a1374b500b1ad27f94199c494f1f68 100644 (file)
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -118,13 +118,6 @@
 #define CSW_MASTER_DEBUG       (1 << 29)               /* ? */
 #define CSW_DBGSWENABLE                (1 << 31)
 
-/* transaction mode */
-#define TRANS_MODE_NONE                        0
-/* Transaction waits for previous to complete */
-#define TRANS_MODE_ATOMIC              1
-/* Freerunning transactions with delays and overrun checking */
-#define TRANS_MODE_COMPOSITE   2
-
 /**
  * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
  * A DAP has two types of component:  one Debug Port (DP), which is a
@@ -138,17 +131,44 @@ struct swjdp_common
        struct arm_jtag *jtag_info;
        /* Control config */
        uint32_t dp_ctrl_stat;
-       /* Support for several AP's in one DAP */
+
+       /**
+        * Cache for DP_SELECT bits identifying the current AP.  A DAP may
+        * connect to multiple APs, such as one MEM-AP for general access,
+        * another reserved for accessing debug modules, and a JTAG-DP.
+        * "-1" indicates no cached value.
+        */
        uint32_t apsel;
-       /* Register select cache */
-       uint32_t dp_select_value;
+
+       /**
+        * Cache for DP_SELECT bits identifying the current four-word AP
+        * register bank.  This caches AP register addresss bits 7:4; JTAG
+        * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
+        * "-1" indicates no cached value.
+        */
+       uint32_t ap_bank_value;
+
+       /**
+        * Cache for (MEM-AP) AP_REG_CSW register value.  This is written to
+        * configure an access mode, such as autoincrementing AP_REG_TAR during
+        * word access.  "-1" indicates no cached value.
+        */
        uint32_t ap_csw_value;
+
+       /**
+        * Cache for (MEM-AP) AP_REG_TAR register value This is written to
+        * configure the address being read or written
+        * "-1" indicates no cached value.
+        */
        uint32_t ap_tar_value;
+
        /* information about current pending SWjDP-AHBAP transaction */
-       uint8_t  trans_mode;
-       uint8_t  trans_rw;
        uint8_t  ack;
-       /* extra tck clocks for memory bus access */
+
+       /**
+        * Configures how many extra tck clocks are added after starting a
+        * MEM-AP access before we try to read its status (and/or result).
+        */
        uint32_t        memaccess_tck;
        /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
        uint32_t tar_autoincr_block;
@@ -164,7 +184,7 @@ static inline uint8_t dap_ap_get_select(struct swjdp_common *swjdp)
 /* AP selection applies to future AP transactions */
 void dap_ap_select(struct swjdp_common *dap,uint8_t apsel);
 
-/* AP transactions ... synchronous given TRANS_MODE_ATOMIC */
+/* Queued AP transactions */
 int dap_setup_accessport(struct swjdp_common *swjdp,
                uint32_t csw, uint32_t tar);
 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
@@ -215,4 +235,12 @@ DAP_COMMAND_HANDLER(dap_memaccess_command);
 DAP_COMMAND_HANDLER(dap_apsel_command);
 DAP_COMMAND_HANDLER(dap_apid_command);
 
+struct target;
+
+/* Put debug link into SWD mode */
+int dap_to_swd(struct target *target);
+
+/* Put debug link into JTAG mode */
+int dap_to_jtag(struct target *target);
+
 #endif