Support for Arm VFP v3 registers read/write

[openocd.git] / src / target / arm_adi_v5.h

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 44d3962cd3660cc7ccd4801139a2f42bbece5f84..657427b25f368d5b61eea8dcadd98a23ed4124ef 100644 (file)
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -16,13 +16,11 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
-#ifndef ARM_ADI_V5_H
-#define ARM_ADI_V5_H
+#ifndef OPENOCD_TARGET_ARM_ADI_V5_H
+#define OPENOCD_TARGET_ARM_ADI_V5_H
 
 /**
  * @file
@@ -34,12 +32,6 @@
 #include <helper/list.h>
 #include "arm_jtag.h"
 
-/* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
- * is no longer JTAG-specific
- */
-#define JTAG_DP_DPACC          0xA
-#define JTAG_DP_APACC          0xB
-
 /* three-bit ACK values for SWD access (sent LSB first) */
 #define SWD_ACK_OK    0x1
 #define SWD_ACK_WAIT  0x2
@@ -53,18 +45,21 @@
 /* A[3:0] for DP registers; A[1:0] are always zero.
  * - JTAG accesses all of these via JTAG_DP_DPACC, except for
  *   IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
- * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
+ * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
  */
-#define DP_IDCODE              BANK_REG(0x0, 0x0)      /* SWD: read */
-#define DP_ABORT               BANK_REG(0x0, 0x0)      /* SWD: write */
-#define DP_CTRL_STAT           BANK_REG(0x0, 0x4)      /* r/w */
-#define DP_RESEND              BANK_REG(0x0, 0x8)      /* SWD: read */
-#define DP_SELECT              BANK_REG(0x0, 0x8)      /* JTAG: r/w; SWD: write */
-#define DP_RDBUFF              BANK_REG(0x0, 0xC)      /* read-only */
-#define DP_WCR                 BANK_REG(0x1, 0x4)      /* SWD: r/w */
-
-#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8)))   /* 1..4 clocks */
-#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr))))         /* impl defined */
+#define DP_DPIDR        BANK_REG(0x0, 0x0) /* DPv1+: ro */
+#define DP_ABORT        BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
+#define DP_CTRL_STAT    BANK_REG(0x0, 0x4) /* DPv0+: rw */
+#define DP_DLCR         BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
+#define DP_TARGETID     BANK_REG(0x2, 0x4) /* DPv2: ro */
+#define DP_DLPIDR       BANK_REG(0x3, 0x4) /* DPv2: ro */
+#define DP_EVENTSTAT    BANK_REG(0x4, 0x4) /* DPv2: ro */
+#define DP_RESEND       BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
+#define DP_SELECT       BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
+#define DP_RDBUFF       BANK_REG(0x0, 0xC) /* DPv0+: ro */
+#define DP_TARGETSEL    BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
+
+#define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
 
 /* Fields of the DP's AP ABORT register */
 #define DAPABORT        (1UL << 0)
@@ -107,6 +102,7 @@
 #define AP_REG_IDR                     0xFC            /* RO: Identification Register */
 
 /* Fields of the MEM-AP's CSW register */
+#define CSW_SIZE_MASK          7
 #define CSW_8BIT               0
 #define CSW_16BIT              1
 #define CSW_32BIT              2
@@ -185,6 +181,9 @@ struct adiv5_ap {
 
        /* true if unaligned memory access is not supported by the MEM-AP */
        bool unaligned_access_bad;
+
+       /* true if tar_value is in sync with TAR register */
+       bool tar_valid;
 };
 
 
@@ -274,6 +273,10 @@ struct dap_ops {
 
        /** Executes all queued DAP operations. */
        int (*run)(struct adiv5_dap *dap);
+
+       /** Executes all queued DAP operations but doesn't check
+        * sticky error conditions */
+       int (*sync)(struct adiv5_dap *dap);
 };
 
 /*
@@ -397,6 +400,14 @@ static inline int dap_run(struct adiv5_dap *dap)
        return dap->ops->run(dap);
 }
 
+static inline int dap_sync(struct adiv5_dap *dap)
+{
+       assert(dap->ops != NULL);
+       if (dap->ops->sync)
+               return dap->ops->sync(dap);
+       return ERROR_OK;
+}
+
 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
                                     uint32_t *value)
 {
@@ -469,6 +480,9 @@ struct adiv5_dap *dap_init(void);
 int dap_dp_init(struct adiv5_dap *dap);
 int mem_ap_init(struct adiv5_ap *ap);
 
+/* Invalidate cached DP select and cached TAR and CSW of all APs */
+void dap_invalidate_cache(struct adiv5_dap *dap);
+
 /* Probe the AP for ROM Table location */
 int dap_get_debugbase(struct adiv5_ap *ap,
                        uint32_t *dbgbase, uint32_t *apid);
@@ -497,4 +511,10 @@ int dap_to_jtag(struct target *target);
 
 extern const struct command_registration dap_command_handlers[];
 
-#endif
+struct adiv5_private_config {
+       int ap_num;
+};
+
+extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi);
+
+#endif /* OPENOCD_TARGET_ARM_ADI_V5_H */