uint32_t memaccess_tck;
/* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
uint32_t tar_autoincr_block;
-
};
/**
static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
uint8_t *ack, uint32_t *data)
{
+ assert(dap->ops != NULL);
return dap->ops->queue_idcode_read(dap, ack, data);
}
static inline int dap_queue_dp_read(struct adiv5_dap *dap,
unsigned reg, uint32_t *data)
{
+ assert(dap->ops != NULL);
return dap->ops->queue_dp_read(dap, reg, data);
}
static inline int dap_queue_dp_write(struct adiv5_dap *dap,
unsigned reg, uint32_t data)
{
+ assert(dap->ops != NULL);
return dap->ops->queue_dp_write(dap, reg, data);
}
static inline int dap_queue_ap_read(struct adiv5_dap *dap,
unsigned reg, uint32_t *data)
{
+ assert(dap->ops != NULL);
return dap->ops->queue_ap_read(dap, reg, data);
}
static inline int dap_queue_ap_write(struct adiv5_dap *dap,
unsigned reg, uint32_t data)
{
+ assert(dap->ops != NULL);
return dap->ops->queue_ap_write(dap, reg, data);
}
*/
static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
{
+ assert(dap->ops != NULL);
return dap->ops->queue_ap_abort(dap, ack);
}
*/
static inline int dap_run(struct adiv5_dap *dap)
{
+ assert(dap->ops != NULL);
return dap->ops->run(dap);
}
/* Initialisation of the debug system, power domains and registers */
int ahbap_debugport_init(struct adiv5_dap *swjdp);
+/* Probe the AP for ROM Table location */
+int dap_get_debugbase(struct adiv5_dap *dap, int apsel,
+ uint32_t *dbgbase, uint32_t *apid);
+
+/* Lookup CoreSight component */
+int dap_lookup_cs_component(struct adiv5_dap *dap, int apsel,
+ uint32_t dbgbase, uint8_t type, uint32_t *addr);
struct target;