arm_adi_v5: Add convenience "atomic"" function for DP reads

[openocd.git] / src / target / arm_adi_v5.h

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 7cc90b241521ee77e5939244404eb4d9f289d049..9f0dea9119186466e38f2f389c0f6f89290ba71e 100644 (file)
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -60,8 +60,8 @@
 #define DP_SELECT              0x8             /* JTAG: r/w; SWD: write */
 #define DP_RDBUFF              0xC             /* read-only */
 
-#define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8))       /* 1..4 clocks */
-#define WCR_TO_PRESCALE(wcr) (7 & ((wcr)))             /* impl defined */
+#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8)))   /* 1..4 clocks */
+#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr))))         /* impl defined */
 
 /* Fields of the DP's AP ABORT register */
 #define DAPABORT               (1 << 0)
@@ -189,6 +189,15 @@ struct adiv5_dap {
 
        /* true if packed transfers are supported by the MEM-AP */
        bool packed_transfers;
+
+       /* true if unaligned memory access is not supported by the MEM-AP */
+       bool unaligned_access_bad;
+
+       /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
+        * despite lack of support in the ARMv7 architecture. Memory access through
+        * the AHB-AP has strange byte ordering these processors, and we need to
+        * swizzle appropriately. */
+       bool ti_be_32_quirks;
 };
 
 /**
@@ -380,6 +389,18 @@ static inline int dap_run(struct adiv5_dap *dap)
        return dap->ops->run(dap);
 }
 
+static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
+                                    uint32_t *value)
+{
+       int retval;
+
+       retval = dap_queue_dp_read(dap, reg, value);
+       if (retval != ERROR_OK)
+               return retval;
+
+       return dap_run(dap);
+}
+
 /** Accessor for currently selected DAP-AP number (0..255) */
 static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
 {
@@ -403,21 +424,6 @@ int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
 int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
                uint32_t address, uint32_t value);
 
-/* MEM-AP memory mapped bus block transfers */
-int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
-               uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
-               uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
-               uint8_t *buffer, int count, uint32_t address, bool addr_incr);
-
-int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
-               const uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
-               const uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
-               const uint8_t *buffer, int count, uint32_t address, bool addr_incr);
-
 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
                uint32_t address, uint32_t *value);
@@ -430,26 +436,24 @@ int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
                uint32_t address, uint32_t value);
 
-/* Non incrementing buffer functions for accessing fifos */
-int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
-               uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
-               const uint8_t *buffer, int count, uint32_t address);
-
-/* MEM-AP memory mapped bus block transfers with selection of ap */
-int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
-               uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
-               uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
-               uint8_t *buffer, int count, uint32_t address);
-
-int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
-               const uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
-               const uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
-               const uint8_t *buffer, int count, uint32_t address);
+/* Synchronous MEM-AP memory mapped bus block transfers */
+int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size,
+               uint32_t count, uint32_t address, bool addrinc);
+int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size,
+               uint32_t count, uint32_t address, bool addrinc);
+
+/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
+int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
+               uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
+int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
+               const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
+
+/* Synchronous, non-incrementing buffer functions for accessing fifos, with
+ * selection of ap */
+int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
+               uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
+int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
+               const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
 
 /* Initialisation of the debug system, power domains and registers */
 int ahbap_debugport_init(struct adiv5_dap *swjdp);