ARM11: use shared DSCR bit names

[openocd.git] / src / target / arm_disassembler.c

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 35c3520306c04d89aa2e72da79d56263208c4d96..29ca23cae1273c4b28f7af6eece027700db58c0a 100644 (file)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -25,7 +25,7 @@
 
 #include "target.h"
 #include "arm_disassembler.h"
-#include "log.h"
+#include <helper/log.h>
 
 
 /*
@@ -1784,8 +1784,12 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode,
        }
 
        /* TODO: deal correctly with dual opcode (prefixed) BL/BLX;
-        * these are effectively 32-bit instructions even in Thumb1.
-        * Might be simplest to always use the Thumb2 decoder.
+        * these are effectively 32-bit instructions even in Thumb1.  For
+        * disassembly, it's simplest to always use the Thumb2 decoder.
+        *
+        * But some cores will evidently handle them as two instructions,
+        * where exceptions may occur between the two.  The ETMv3.2+ ID
+        * register has a bit which exposes this behavior.
         */
 
        snprintf(instruction->text, 128,