target/arm_disassembler: add exception related disassembly

[openocd.git] / src / target / arm_disassembler.c

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index f11a5221a15968d0619f955fe1b7c7c0941d0c0a..65086c2fdd4752d8dd5c2080b5043c0c3a29cc2a 100644 (file)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -17,7 +17,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -1403,17 +1403,46 @@ static int evaluate_misc_instr(uint32_t opcode,
                                Rn);
        }
 
-       /* Software breakpoints */
+       /* exception return */
+       if ((opcode & 0x0000000f0) == 0x00000060) {
+               if (((opcode & 0x600000) >> 21) == 3)
+                       instruction->type = ARM_ERET;
+               snprintf(instruction->text,
+                               128,
+                               "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tERET",
+                               address,
+                               opcode);
+       }
+
+       /* exception generate instructions */
        if ((opcode & 0x0000000f0) == 0x00000070) {
-               uint32_t immediate;
-               instruction->type = ARM_BKPT;
-               immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
+               uint32_t immediate = 0;
+               char *mnemonic = NULL;
+
+               switch ((opcode & 0x600000) >> 21) {
+                       case 0x1:
+                               instruction->type = ARM_BKPT;
+                               mnemonic = "BRKT";
+                               immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
+                               break;
+                       case 0x2:
+                               instruction->type = ARM_HVC;
+                               mnemonic = "HVC";
+                               immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
+                               break;
+                       case 0x3:
+                               instruction->type = ARM_SMC;
+                               mnemonic = "SMC";
+                               immediate = (opcode & 0xf);
+                               break;
+               }
 
                snprintf(instruction->text,
                                128,
-                               "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBKPT 0x%4.4" PRIx32 "",
+                               "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s 0x%4.4" PRIx32 "",
                                address,
                                opcode,
+                               mnemonic,
                                immediate);
        }
 
@@ -2890,7 +2919,7 @@ static int t2ev_cond_b(uint32_t opcode, uint32_t address,
        offset = opcode & 0x7ff;
        offset |= (opcode & 0x003f0000) >> 5;
        if (opcode & (1 << 26)) {
-               offset |= 0xffff << 19;
+               offset |= 0x1fff << 19;
                if ((opcode & (1 << 11)) == 0)
                        b17 = 0;
                if ((opcode & (1 << 13)) == 0)