- Fixes '!=' whitespace

[openocd.git] / src / target / arm_disassembler.c

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 7028e9f515c0b1ed1a25013e597a86c899f54bd4..90442ea8a96fc667637103ab4ff204103ee2618b 100644 (file)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -22,10 +22,8 @@
 #endif
 
 #include "arm_disassembler.h"
-
 #include "log.h"
 
-#include <string.h>
 
 /* textual represenation of the condition field */
 /* ALways (default) is ommitted (empty string) */
@@ -35,19 +33,19 @@ char *arm_condition_strings[] =
 };
 
 /* make up for C's missing ROR */
-u32 ror(u32 value, int places) 
+uint32_t ror(uint32_t value, int places) 
 { 
        return (value >> places) | (value << (32 - places)); 
 }
 
-int evaluate_pld(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_pld(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
        /* PLD */
        if ((opcode & 0x0d70f0000) == 0x0550f000)
        {
                instruction->type = ARM_PLD;
                
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tPLD ...TODO...", address, opcode);
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD ...TODO...", address, opcode);
                
                return ERROR_OK;
        }
@@ -57,24 +55,24 @@ int evaluate_pld(u32 opcode, u32 address, arm_instruction_t *instruction)
                return ERROR_OK;
        }
        
-       ERROR("should never reach this point");
+       LOG_ERROR("should never reach this point");
        return -1;
 }
 
-int evaluate_swi(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_swi(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
        instruction->type = ARM_SWI;
        
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSWI 0x%6.6x", address, opcode, (opcode & 0xffffff));
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSWI 0x%6.6" PRIx32 "", address, opcode, (opcode & 0xffffff));
        
        return ERROR_OK;
 }
 
-int evaluate_blx_imm(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_blx_imm(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
        int offset;
-       u32 immediate;
-       u32 target_address;
+       uint32_t immediate;
+       uint32_t target_address;
        
        instruction->type = ARM_BLX;
        immediate = opcode & 0x00ffffff;
@@ -94,7 +92,7 @@ int evaluate_blx_imm(u32 opcode, u32 address, arm_instruction_t *instruction)
        
        target_address = address + 8 + offset;
        
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBLX 0x%8.8x", address, opcode, target_address);
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32 "", address, opcode, target_address);
        
        instruction->info.b_bl_bx_blx.reg_operand = -1;
        instruction->info.b_bl_bx_blx.target_address = target_address;
@@ -102,12 +100,12 @@ int evaluate_blx_imm(u32 opcode, u32 address, arm_instruction_t *instruction)
        return ERROR_OK;
 }
 
-int evaluate_b_bl(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_b_bl(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 L;
-       u32 immediate;
+       uint8_t L;
+       uint32_t immediate;
        int offset;
-       u32 target_address;
+       uint32_t target_address;
        
        immediate = opcode & 0x00ffffff;
        L = (opcode & 0x01000000) >> 24;
@@ -128,7 +126,7 @@ int evaluate_b_bl(u32 opcode, u32 address, arm_instruction_t *instruction)
        else
                instruction->type = ARM_B;
        
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tB%s%s 0x%8.8x", address, opcode,
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tB%s%s 0x%8.8" PRIx32 , address, opcode,
                         (L) ? "L" : "", COND(opcode), target_address);
        
        instruction->info.b_bl_bx_blx.reg_operand = -1;
@@ -139,14 +137,14 @@ int evaluate_b_bl(u32 opcode, u32 address, arm_instruction_t *instruction)
 
 /* Coprocessor load/store and double register transfers */
 /* both normal and extended instruction space (condition field b1111) */
-int evaluate_ldc_stc_mcrr_mrrc(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 cp_num = (opcode & 0xf00) >> 8;
+       uint8_t cp_num = (opcode & 0xf00) >> 8;
        
        /* MCRR or MRRC */
        if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c400000))
        {
-               u8 cp_opcode, Rd, Rn, CRm;
+               uint8_t cp_opcode, Rd, Rn, CRm;
                char *mnemonic;
                
                cp_opcode = (opcode & 0xf0) >> 4;
@@ -168,13 +166,13 @@ int evaluate_ldc_stc_mcrr_mrrc(u32 opcode, u32 address, arm_instruction_t *instr
                        mnemonic = "MRRC";
                }
                
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s p%i, %x, r%i, r%i, c%i",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, %x, r%i, r%i, c%i",
                                 address, opcode, mnemonic, COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm);
        }
        else /* LDC or STC */
        {
-               u8 CRd, Rn, offset;
-               u8 U, N;
+               uint8_t CRd, Rn, offset;
+               uint8_t U, N;
                char *mnemonic;
                char addressing_mode[32];
                
@@ -207,7 +205,7 @@ int evaluate_ldc_stc_mcrr_mrrc(u32 opcode, u32 address, arm_instruction_t *instr
                else if ((opcode & 0x01200000) == 0x00000000) /* unindexed */
                        snprintf(addressing_mode, 32, "[r%i], #0x%2.2x", Rn, offset);
 
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s p%i, c%i, %s",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s p%i, c%i, %s",
                                 address, opcode, mnemonic, ((opcode & 0xf0000000) == 0xf0000000) ? COND(opcode) : "2",
                                 (N) ? "L" : "",
                                 cp_num, CRd, addressing_mode);
@@ -219,11 +217,11 @@ int evaluate_ldc_stc_mcrr_mrrc(u32 opcode, u32 address, arm_instruction_t *instr
 /* Coprocessor data processing instructions */
 /* Coprocessor register transfer instructions */
 /* both normal and extended instruction space (condition field b1111) */
-int evaluate_cdp_mcr_mrc(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_cdp_mcr_mrc(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
        char* cond;
        char* mnemonic;
-       u8 cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2;
+       uint8_t cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2;
        
        cond = ((opcode & 0xf0000000) == 0xf0000000) ? "2" : COND(opcode);
        cp_num = (opcode & 0xf00) >> 8;
@@ -248,7 +246,7 @@ int evaluate_cdp_mcr_mrc(u32 opcode, u32 address, arm_instruction_t *instruction
                
                opcode_1 = (opcode & 0x00e00000) >> 21;
                
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s p%i, 0x%2.2x, r%i, c%i, c%i, 0x%2.2x",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, r%i, c%i, c%i, 0x%2.2x",
                                 address, opcode, mnemonic, cond,
                                 cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2);
        }
@@ -259,7 +257,7 @@ int evaluate_cdp_mcr_mrc(u32 opcode, u32 address, arm_instruction_t *instruction
                
                opcode_1 = (opcode & 0x00f00000) >> 20;
                
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s p%i, 0x%2.2x, c%i, c%i, c%i, 0x%2.2x",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, c%i, c%i, c%i, 0x%2.2x",
                                 address, opcode, mnemonic, cond,
                                 cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2);
        }
@@ -268,10 +266,10 @@ int evaluate_cdp_mcr_mrc(u32 opcode, u32 address, arm_instruction_t *instruction
 }
 
 /* Load/store instructions */
-int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 I, P, U, B, W, L;
-       u8 Rn, Rd;
+       uint8_t I, P, U, B, W, L;
+       uint8_t Rn, Rd;
        char *operation; /* "LDR" or "STR" */
        char *suffix; /* "", "B", "T", "BT" */
        char offset[32];
@@ -342,9 +340,9 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
        
        if (!I) /* #+-<offset_12> */
        {
-               u32 offset_12 = (opcode & 0xfff);
+               uint32_t offset_12 = (opcode & 0xfff);
                if (offset_12)
-                       snprintf(offset, 32, ", #%s0x%x", (U) ? "" : "-", offset_12);
+                       snprintf(offset, 32, ", #%s0x%" PRIx32 "", (U) ? "" : "-", offset_12);
                else
                        snprintf(offset, 32, "%s", "");
                
@@ -353,8 +351,8 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
        }
        else /* either +-<Rm> or +-<Rm>, <shift>, #<shift_imm> */
        {
-               u8 shift_imm, shift;
-               u8 Rm;
+               uint8_t shift_imm, shift;
+               uint8_t Rm;
                
                shift_imm = (opcode & 0xf80) >> 7;
                shift = (opcode & 0x60) >> 5;
@@ -408,7 +406,7 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
        {
                if (W == 0) /* offset */
                {
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i%s]",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]",
                                         address, opcode, operation, COND(opcode), suffix,
                                         Rd, Rn, offset);
                        
@@ -416,7 +414,7 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
                }
                else /* pre-indexed */
                {
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i%s]!",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]!",
                                         address, opcode, operation, COND(opcode), suffix,
                                         Rd, Rn, offset);
                        
@@ -425,7 +423,7 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
        }
        else /* post-indexed */
        {
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i]%s",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i]%s",
                                 address, opcode, operation, COND(opcode), suffix,
                                 Rd, Rn, offset);
                
@@ -436,10 +434,10 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
 }
 
 /* Miscellaneous load/store instructions */
-int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 P, U, I, W, L, S, H;
-       u8 Rn, Rd;
+       uint8_t P, U, I, W, L, S, H;
+       uint8_t Rn, Rd;
        char *operation; /* "LDR" or "STR" */
        char *suffix; /* "H", "SB", "SH", "D" */
        char offset[32];
@@ -513,15 +511,15 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
        
        if (I) /* Immediate offset/index (#+-<offset_8>)*/
        {
-               u32 offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
-               snprintf(offset, 32, "#%s0x%x", (U) ? "" : "-", offset_8);
+               uint32_t offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
+               snprintf(offset, 32, "#%s0x%" PRIx32 "", (U) ? "" : "-", offset_8);
                
                instruction->info.load_store.offset_mode = 0;
                instruction->info.load_store.offset.offset = offset_8;
        }
        else /* Register offset/index (+-<Rm>) */
        {
-               u8 Rm;
+               uint8_t Rm;
                Rm = (opcode & 0xf);
                snprintf(offset, 32, "%sr%i", (U) ? "" : "-", Rm);
                
@@ -535,7 +533,7 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
        {
                if (W == 0) /* offset */
                {
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i, %s]",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]",
                                         address, opcode, operation, COND(opcode), suffix,
                                         Rd, Rn, offset);
                        
@@ -543,7 +541,7 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
                }
                else /* pre-indexed */
                {
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i, %s]!",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]!",
                                         address, opcode, operation, COND(opcode), suffix,
                                         Rd, Rn, offset);
                
@@ -552,7 +550,7 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
        }
        else /* post-indexed */
        {
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i], %s",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i], %s",
                                 address, opcode, operation, COND(opcode), suffix,
                                 Rd, Rn, offset);
        
@@ -563,10 +561,10 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
 }
 
 /* Load/store multiples instructions */
-int evaluate_ldm_stm(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_ldm_stm(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 P, U, S, W, L, Rn;
-       u32 register_list;
+       uint8_t P, U, S, W, L, Rn;
+       uint32_t register_list;
        char *addressing_mode;
        char *mnemonic;
        char reg_list[69];
@@ -642,7 +640,7 @@ int evaluate_ldm_stm(u32 opcode, u32 address, arm_instruction_t *instruction)
                }
        }
        
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i%s, {%s}%s",
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i%s, {%s}%s",
                         address, opcode, mnemonic, COND(opcode), addressing_mode,
                         Rn, (W) ? "!" : "", reg_list, (S) ? "^" : "");
        
@@ -650,7 +648,7 @@ int evaluate_ldm_stm(u32 opcode, u32 address, arm_instruction_t *instruction)
 }
 
 /* Multiplies, extra load/stores */
-int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_mul_and_extra_ld_st(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
        /* Multiply (accumulate) (long) and Swap/swap byte */
        if ((opcode & 0x000000f0) == 0x00000090)
@@ -658,7 +656,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
                /* Multiply (accumulate) */
                if ((opcode & 0x0f800000) == 0x00000000)
                {
-                       u8 Rm, Rs, Rn, Rd, S;
+                       uint8_t Rm, Rs, Rn, Rd, S;
                        Rm = opcode & 0xf;
                        Rs = (opcode & 0xf00) >> 8;
                        Rn = (opcode & 0xf000) >> 12;
@@ -669,13 +667,13 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
                        if (opcode & 0x00200000)
                        {
                                instruction->type = ARM_MLA;
-                               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMLA%s%s r%i, r%i, r%i, r%i",
+                               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMLA%s%s r%i, r%i, r%i, r%i",
                                                address, opcode, COND(opcode), (S) ? "S" : "", Rd, Rm, Rs, Rn);
                        }
                        else
                        {
                                instruction->type = ARM_MUL;
-                               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMUL%s%s r%i, r%i, r%i",
+                               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMUL%s%s r%i, r%i, r%i",
                                                 address, opcode, COND(opcode), (S) ? "S" : "", Rd, Rm, Rs);
                        }
                        
@@ -686,7 +684,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
                if ((opcode & 0x0f800000) == 0x00800000)
                {
                        char* mnemonic = NULL;
-                       u8 Rm, Rs, RdHi, RdLow, S;
+                       uint8_t Rm, Rs, RdHi, RdLow, S;
                        Rm = opcode & 0xf;
                        Rs = (opcode & 0xf00) >> 8;
                        RdHi = (opcode & 0xf000) >> 12;
@@ -713,7 +711,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
                                        break;
                        }
                        
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, r%i, r%i, r%i",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, r%i, r%i",
                                                address, opcode, mnemonic, COND(opcode), (S) ? "S" : "",
                                                RdLow, RdHi, Rm, Rs);
                        
@@ -723,7 +721,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
                /* Swap/swap byte */
                if ((opcode & 0x0f800000) == 0x01000000)
                {
-                       u8 Rm, Rd, Rn;
+                       uint8_t Rm, Rd, Rn;
                        Rm = opcode & 0xf;
                        Rd = (opcode & 0xf000) >> 12;
                        Rn = (opcode & 0xf0000) >> 16;
@@ -731,7 +729,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
                        /* examine B flag */
                        instruction->type = (opcode & 0x00400000) ? ARM_SWPB : ARM_SWP;
                        
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s r%i, r%i, [r%i]",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, [r%i]",
                                         address, opcode, (opcode & 0x00400000) ? "SWPB" : "SWP", COND(opcode), Rd, Rm, Rn);
                        return ERROR_OK;
                }
@@ -741,7 +739,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
        return evaluate_misc_load_store(opcode, address, instruction);
 }
 
-int evaluate_mrs_msr(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_mrs_msr(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
        int R = (opcode & 0x00400000) >> 22;
        char *PSR = (R) ? "SPSR" : "CPSR";
@@ -754,10 +752,10 @@ int evaluate_mrs_msr(u32 opcode, u32 address, arm_instruction_t *instruction)
                /* immediate variant */
                if (opcode & 0x02000000)
                {
-                       u8 immediate = (opcode & 0xff);
-                       u8 rotate = (opcode & 0xf00);
+                       uint8_t immediate = (opcode & 0xff);
+                       uint8_t rotate = (opcode & 0xf00);
                        
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMSR%s %s_%s%s%s%s, 0x%8.8x",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, 0x%8.8" PRIx32 ,
                                         address, opcode, COND(opcode), PSR,
                                         (opcode & 0x10000) ? "c" : "",
                                         (opcode & 0x20000) ? "x" : "",
@@ -768,8 +766,8 @@ int evaluate_mrs_msr(u32 opcode, u32 address, arm_instruction_t *instruction)
                }
                else /* register variant */
                {
-                       u8 Rm = opcode & 0xf;
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMSR%s %s_%s%s%s%s, r%i",
+                       uint8_t Rm = opcode & 0xf;
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, r%i",
                                         address, opcode, COND(opcode), PSR,
                                         (opcode & 0x10000) ? "c" : "",
                                         (opcode & 0x20000) ? "x" : "",
@@ -782,12 +780,12 @@ int evaluate_mrs_msr(u32 opcode, u32 address, arm_instruction_t *instruction)
        }
        else /* Move status register to register (MRS) */
        {
-               u8 Rd;
+               uint8_t Rd;
                
                instruction->type = ARM_MRS;
                Rd = (opcode & 0x0000f000) >> 12;
                        
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMRS%s r%i, %s",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMRS%s r%i, %s",
                                 address, opcode, COND(opcode), Rd, PSR);
        }
        
@@ -795,7 +793,7 @@ int evaluate_mrs_msr(u32 opcode, u32 address, arm_instruction_t *instruction)
 }
 
 /* Miscellaneous instructions */
-int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
        /* MRS/MSR */
        if ((opcode & 0x000000f0) == 0x00000000)
@@ -806,11 +804,11 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
        /* BX */
        if ((opcode & 0x006000f0) == 0x00200010)
        {
-               u8 Rm;
+               uint8_t Rm;
                instruction->type = ARM_BX;
                Rm = opcode & 0xf;
                
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBX%s r%i",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBX%s r%i",
                                 address, opcode, COND(opcode), Rm);
                
                instruction->info.b_bl_bx_blx.reg_operand = Rm;
@@ -818,25 +816,25 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
        }
        
        /* CLZ */
-       if ((opcode & 0x0060000f0) == 0x00300010)
+       if ((opcode & 0x006000f0) == 0x00600010)
        {
-               u8 Rm, Rd;
+               uint8_t Rm, Rd;
                instruction->type = ARM_CLZ;
                Rm = opcode & 0xf;
                Rd = (opcode & 0xf000) >> 12;
 
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tCLZ%s r%i, r%i",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tCLZ%s r%i, r%i",
                                 address, opcode, COND(opcode), Rd, Rm);
        }
        
-       /* BLX */
-       if ((opcode & 0x0060000f0) == 0x00200030)
+       /* BLX(2) */
+       if ((opcode & 0x006000f0) == 0x00200030)
        {
-               u8 Rm;
+               uint8_t Rm;
                instruction->type = ARM_BLX;
                Rm = opcode & 0xf;
                
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBLX%s r%i",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX%s r%i",
                                 address, opcode, COND(opcode), Rm);
                                 
                instruction->info.b_bl_bx_blx.reg_operand = Rm;
@@ -846,7 +844,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
        /* Enhanced DSP add/subtracts */
        if ((opcode & 0x0000000f0) == 0x00000050)
        {
-               u8 Rm, Rd, Rn;
+               uint8_t Rm, Rd, Rn;
                char *mnemonic = NULL;
                Rm = opcode & 0xf;
                Rd = (opcode & 0xf000) >> 12;
@@ -872,18 +870,18 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
                                break;
                }
                
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s r%i, r%i, r%i",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, r%i",
                                 address, opcode, mnemonic, COND(opcode), Rd, Rm, Rn);
        }
        
        /* Software breakpoints */
        if ((opcode & 0x0000000f0) == 0x00000070)
        {
-               u32 immediate;
+               uint32_t immediate;
                instruction->type = ARM_BKPT;
                immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
                
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBKPT 0x%4.4x",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBKPT 0x%4.4" PRIx32 "",
                                 address, opcode, immediate);   
        }
        
@@ -896,14 +894,14 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
                /* SMLA<x><y> */
                if ((opcode & 0x00600000) == 0x00000000)
                {
-                       u8 Rd, Rm, Rs, Rn;
+                       uint8_t Rd, Rm, Rs, Rn;
                        instruction->type = ARM_SMLAxy;
                        Rd = (opcode & 0xf0000) >> 16;
                        Rm = (opcode & 0xf);
                        Rs = (opcode & 0xf00) >> 8;
                        Rn = (opcode & 0xf000) >> 12;
                        
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSMLA%s%s%s r%i, r%i, r%i, r%i",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i",
                                         address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
                                         Rd, Rm, Rs, Rn);
                }
@@ -911,14 +909,14 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
                /* SMLAL<x><y> */
                if ((opcode & 0x00600000) == 0x00400000)
                {
-                       u8 RdLow, RdHi, Rm, Rs;
+                       uint8_t RdLow, RdHi, Rm, Rs;
                        instruction->type = ARM_SMLAxy;
                        RdHi = (opcode & 0xf0000) >> 16;
                        RdLow = (opcode & 0xf000) >> 12;
                        Rm = (opcode & 0xf);
                        Rs = (opcode & 0xf00) >> 8;
                        
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSMLA%s%s%s r%i, r%i, r%i, r%i",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i",
                                         address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
                                         RdLow, RdHi, Rm, Rs);
                }
@@ -926,14 +924,14 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
                /* SMLAW<y> */
                if (((opcode & 0x00600000) == 0x00100000) && (x == 0))
                {
-                       u8 Rd, Rm, Rs, Rn;
+                       uint8_t Rd, Rm, Rs, Rn;
                        instruction->type = ARM_SMLAWy;
                        Rd = (opcode & 0xf0000) >> 16;
                        Rm = (opcode & 0xf);
                        Rs = (opcode & 0xf00) >> 8;
                        Rn = (opcode & 0xf000) >> 12;
 
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSMLAW%s%s r%i, r%i, r%i, r%i",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLAW%s%s r%i, r%i, r%i, r%i",
                                         address, opcode, (y) ? "T" : "B", COND(opcode),
                                         Rd, Rm, Rs, Rn);
                }
@@ -941,13 +939,13 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
                /* SMUL<x><y> */
                if ((opcode & 0x00600000) == 0x00300000)
                {
-                       u8 Rd, Rm, Rs;
+                       uint8_t Rd, Rm, Rs;
                        instruction->type = ARM_SMULxy;
                        Rd = (opcode & 0xf0000) >> 16;
                        Rm = (opcode & 0xf);
                        Rs = (opcode & 0xf00) >> 8;
                        
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSMULW%s%s%s r%i, r%i, r%i",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s%s r%i, r%i, r%i",
                                         address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
                                         Rd, Rm, Rs);
                }
@@ -955,13 +953,13 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
                /* SMULW<y> */
                if (((opcode & 0x00600000) == 0x00100000) && (x == 1))
                {
-                       u8 Rd, Rm, Rs;
+                       uint8_t Rd, Rm, Rs;
                        instruction->type = ARM_SMULWy;
                        Rd = (opcode & 0xf0000) >> 16;
                        Rm = (opcode & 0xf);
                        Rs = (opcode & 0xf00) >> 8;
                        
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSMULW%s%s r%i, r%i, r%i",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s r%i, r%i, r%i",
                                         address, opcode, (y) ? "T" : "B", COND(opcode),
                                         Rd, Rm, Rs);
                }
@@ -970,9 +968,9 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
        return ERROR_OK;
 }
 
-int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 I, op, S, Rn, Rd;
+       uint8_t I, op, S, Rn, Rd;
        char *mnemonic = NULL;
        char shifter_operand[32];
        
@@ -1057,26 +1055,26 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
        
        if (I) /* immediate shifter operand (#<immediate>)*/
        {
-               u8 immed_8 = opcode & 0xff;
-               u8 rotate_imm = (opcode & 0xf00) >> 8;
-               u32 immediate;
+               uint8_t immed_8 = opcode & 0xff;
+               uint8_t rotate_imm = (opcode & 0xf00) >> 8;
+               uint32_t immediate;
                
                immediate = ror(immed_8, rotate_imm * 2);
                
-               snprintf(shifter_operand, 32, "#0x%x", immediate);
+               snprintf(shifter_operand, 32, "#0x%" PRIx32 "", immediate);
                
                instruction->info.data_proc.variant = 0;
                instruction->info.data_proc.shifter_operand.immediate.immediate = immediate;
        }
        else /* register-based shifter operand */
        {
-               u8 shift, Rm;
+               uint8_t shift, Rm;
                shift = (opcode & 0x60) >> 5;
                Rm = (opcode & 0xf);
                
                if ((opcode & 0x10) != 0x10) /* Immediate shifts ("<Rm>" or "<Rm>, <shift> #<shift_immediate>") */
                {
-                       u8 shift_imm;
+                       uint8_t shift_imm;
                        shift_imm = (opcode & 0xf80) >> 7;
 
                        instruction->info.data_proc.variant = 1;
@@ -1126,7 +1124,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
                }
                else /* Register shifts ("<Rm>, <shift> <Rs>") */
                {
-                       u8 Rs = (opcode & 0xf00) >> 8;
+                       uint8_t Rs = (opcode & 0xf00) >> 8;
                        
                        instruction->info.data_proc.variant = 2;
                        instruction->info.data_proc.shifter_operand.register_shift.Rm = Rm;
@@ -1154,22 +1152,22 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
        
        if ((op < 0x8) || (op == 0xc) || (op == 0xe)) /* <opcode3>{<cond>}{S} <Rd>, <Rn>, <shifter_operand> */
        {
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, r%i, %s",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, %s",
                                 address, opcode, mnemonic, COND(opcode),
                                 (S) ? "S" : "", Rd, Rn, shifter_operand);
        }
        else if ((op == 0xd) || (op == 0xf)) /* <opcode1>{<cond>}{S} <Rd>, <shifter_operand> */
        {
                if (opcode==0xe1a00000) /* print MOV r0,r0 as NOP */
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tNOP",address, opcode);
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tNOP",address, opcode);
                else
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, %s",
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, %s",
                                 address, opcode, mnemonic, COND(opcode),
                                 (S) ? "S" : "", Rd, shifter_operand);
        }
        else /* <opcode2>{<cond>} <Rn>, <shifter_operand> */
        {
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s r%i, %s",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, %s",
                                 address, opcode, mnemonic, COND(opcode),
                                 Rn, shifter_operand);
        }
@@ -1177,7 +1175,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
        return ERROR_OK;
 }
                
-int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
+int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
        /* clear fields, to avoid confusion */
        memset(instruction, 0, sizeof(arm_instruction_t));
@@ -1194,7 +1192,7 @@ int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
                if ((opcode & 0x0e000000) == 0x08000000)
                {
                        instruction->type = ARM_UNDEFINED_INSTRUCTION;
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
                        return ERROR_OK;
                }
                
@@ -1219,7 +1217,7 @@ int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
                if ((opcode & 0x0f000000) == 0x0f000000)
                {
                        instruction->type = ARM_UNDEFINED_INSTRUCTION;
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
                        return ERROR_OK;
                }
        }
@@ -1245,7 +1243,7 @@ int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
                if ((opcode & 0x0fb00000) == 0x03000000)
                {
                        instruction->type = ARM_UNDEFINED_INSTRUCTION;
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
                        return ERROR_OK;
                }
                                
@@ -1271,7 +1269,7 @@ int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
                if ((opcode & 0x00000010) == 0x00000010)
                {
                        instruction->type = ARM_UNDEFINED_INSTRUCTION;
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
                        return ERROR_OK;
                }
                
@@ -1317,15 +1315,15 @@ int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
                        return evaluate_cdp_mcr_mrc(opcode, address, instruction);
        }
        
-       ERROR("should never reach this point");
+       LOG_ERROR("should never reach this point");
        return -1;
 }
 
-int evaluate_b_bl_blx_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u32 offset = opcode & 0x7ff;
-       u32 opc = (opcode >> 11) & 0x3;
-       u32 target_address;
+       uint32_t offset = opcode & 0x7ff;
+       uint32_t opc = (opcode >> 11) & 0x3;
+       uint32_t target_address;
        char *mnemonic = NULL;
        
        /* sign extend 11-bit offset */
@@ -1334,7 +1332,7 @@ int evaluate_b_bl_blx_thumb(u16 opcode, u32 address, arm_instruction_t *instruct
        
        target_address = address + 4 + (offset<<1);
 
-       switch(opc)
+       switch (opc)
        {
                /* unconditional branch */
                case 0:
@@ -1360,7 +1358,7 @@ int evaluate_b_bl_blx_thumb(u16 opcode, u32 address, arm_instruction_t *instruct
        }
        /* TODO: deals correctly with dual opcodes BL/BLX ... */
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s 0x%8.8x", address, opcode,mnemonic, target_address);
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s 0x%8.8" PRIx32 , address, opcode,mnemonic, target_address);
        
        instruction->info.b_bl_bx_blx.reg_operand = -1;
        instruction->info.b_bl_bx_blx.target_address = target_address;
@@ -1368,13 +1366,13 @@ int evaluate_b_bl_blx_thumb(u16 opcode, u32 address, arm_instruction_t *instruct
        return ERROR_OK;
 }
 
-int evaluate_add_sub_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 Rd = (opcode >> 0) & 0x7;
-       u8 Rn = (opcode >> 3) & 0x7;
-       u8 Rm_imm = (opcode >> 6) & 0x7;
-       u32 opc = opcode & (1<<9);
-       u32 reg_imm  = opcode & (1<<10);
+       uint8_t Rd = (opcode >> 0) & 0x7;
+       uint8_t Rn = (opcode >> 3) & 0x7;
+       uint8_t Rm_imm = (opcode >> 6) & 0x7;
+       uint32_t opc = opcode & (1<<9);
+       uint32_t reg_imm  = opcode & (1<<10);
        char *mnemonic;
        
        if (opc)
@@ -1396,29 +1394,29 @@ int evaluate_add_sub_thumb(u16 opcode, u32 address, arm_instruction_t *instructi
        {
                instruction->info.data_proc.variant = 0; /*immediate*/
                instruction->info.data_proc.shifter_operand.immediate.immediate = Rm_imm;
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, r%i, #%d",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, #%d",
                                 address, opcode, mnemonic, Rd, Rn, Rm_imm);
        }
        else
        {
                instruction->info.data_proc.variant = 1; /*immediate shift*/
                instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm_imm;
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, r%i, r%i",
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, r%i",
                                 address, opcode, mnemonic, Rd, Rn, Rm_imm);
        }
 
        return ERROR_OK;
 }
 
-int evaluate_shift_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_shift_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 Rd = (opcode >> 0) & 0x7;
-       u8 Rm = (opcode >> 3) & 0x7;
-       u8 imm = (opcode >> 6) & 0x1f;
-       u8 opc = (opcode >> 11) & 0x3;
+       uint8_t Rd = (opcode >> 0) & 0x7;
+       uint8_t Rm = (opcode >> 3) & 0x7;
+       uint8_t imm = (opcode >> 6) & 0x1f;
+       uint8_t opc = (opcode >> 11) & 0x3;
        char *mnemonic = NULL;
        
-       switch(opc)
+       switch (opc)
        {
                case 0:
                        instruction->type = ARM_MOV;
@@ -1437,7 +1435,7 @@ int evaluate_shift_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
                        break;
        }
 
-       if ((imm==0) && (opc!=0))
+       if ((imm==0) && (opc != 0))
                imm = 32;
 
        instruction->info.data_proc.Rd = Rd;
@@ -1448,17 +1446,17 @@ int evaluate_shift_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
        instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
        instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm;
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, r%i, #0x%02x",
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, #0x%02x" ,
                                 address, opcode, mnemonic, Rd, Rm, imm);
 
        return ERROR_OK;
 }
 
-int evaluate_data_proc_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_data_proc_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 imm = opcode & 0xff;
-       u8 Rd = (opcode >> 8) & 0x7;
-       u32 opc = (opcode >> 11) & 0x3;
+       uint8_t imm = opcode & 0xff;
+       uint8_t Rd = (opcode >> 8) & 0x7;
+       uint32_t opc = (opcode >> 11) & 0x3;
        char *mnemonic = NULL;
        
        instruction->info.data_proc.Rd = Rd;
@@ -1467,7 +1465,7 @@ int evaluate_data_proc_imm_thumb(u16 opcode, u32 address, arm_instruction_t *ins
        instruction->info.data_proc.variant = 0; /*immediate*/
        instruction->info.data_proc.shifter_operand.immediate.immediate = imm;
        
-       switch(opc)
+       switch (opc)
        {
                case 0:
                        instruction->type = ARM_MOV;
@@ -1489,15 +1487,15 @@ int evaluate_data_proc_imm_thumb(u16 opcode, u32 address, arm_instruction_t *ins
                        break;
        }
        
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, #0x%02x",
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, #0x%02x" ,
                                 address, opcode, mnemonic, Rd, imm);
 
        return ERROR_OK;
 }
 
-int evaluate_data_proc_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 high_reg, op, Rm, Rd,H1,H2;
+       uint8_t high_reg, op, Rm, Rd,H1,H2;
        char *mnemonic = NULL;
        
        high_reg = (opcode & 0x0400) >> 10;
@@ -1541,18 +1539,18 @@ int evaluate_data_proc_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
                                        if (H1)
                                        {
                                                instruction->type = ARM_BLX;
-                                               snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tBLX r%i", address, opcode, Rm);
+                                               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBLX r%i", address, opcode, Rm);
                                        }
                                        else
                                        {
                                                instruction->type = ARM_BX;
-                                               snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tBX r%i", address, opcode, Rm);
+                                               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBX r%i", address, opcode, Rm);
                                        }
                                }
                                else
                                {
                                        instruction->type = ARM_UNDEFINED_INSTRUCTION;
-                                       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
+                                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
                                }
                                return ERROR_OK;        
                                break;
@@ -1648,21 +1646,21 @@ int evaluate_data_proc_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
                }
        }
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, r%i",
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i",
                                 address, opcode, mnemonic, Rd, Rm);
 
        return ERROR_OK;
 }
 
-int evaluate_load_literal_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_load_literal_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u32 immediate;
-       u8 Rd = (opcode >> 8) & 0x7; 
+       uint32_t immediate;
+       uint8_t Rd = (opcode >> 8) & 0x7; 
 
        instruction->type = ARM_LDR;
        immediate = opcode & 0x000000ff;
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tLDR r%i, [PC, #0x%x]", address, opcode, Rd, immediate*4);
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tLDR r%i, [PC, #0x%" PRIx32 "]", address, opcode, Rd, immediate*4);
 
        instruction->info.load_store.Rd = Rd;
        instruction->info.load_store.Rn = 15 /*PC*/;
@@ -1673,15 +1671,15 @@ int evaluate_load_literal_thumb(u16 opcode, u32 address, arm_instruction_t *inst
        return ERROR_OK;
 }
 
-int evaluate_load_store_reg_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_load_store_reg_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u8 Rd = (opcode >> 0) & 0x7; 
-       u8 Rn = (opcode >> 3) & 0x7; 
-       u8 Rm = (opcode >> 6) & 0x7; 
-       u8 opc = (opcode >> 9) & 0x7; 
+       uint8_t Rd = (opcode >> 0) & 0x7; 
+       uint8_t Rn = (opcode >> 3) & 0x7; 
+       uint8_t Rm = (opcode >> 6) & 0x7; 
+       uint8_t opc = (opcode >> 9) & 0x7; 
        char *mnemonic = NULL;
 
-       switch(opc)
+       switch (opc)
        {
                case 0:
                        instruction->type = ARM_STR;
@@ -1717,7 +1715,7 @@ int evaluate_load_store_reg_thumb(u16 opcode, u32 address, arm_instruction_t *in
                        break;
        }
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, [r%i, r%i]", address, opcode, mnemonic, Rd, Rn, Rm);
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [r%i, r%i]", address, opcode, mnemonic, Rd, Rn, Rm);
        
        instruction->info.load_store.Rd = Rd;
        instruction->info.load_store.Rn = Rn;
@@ -1728,16 +1726,16 @@ int evaluate_load_store_reg_thumb(u16 opcode, u32 address, arm_instruction_t *in
        return ERROR_OK;
 }
 
-int evaluate_load_store_imm_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u32 offset = (opcode >> 6) & 0x1f;
-       u8 Rd = (opcode >> 0) & 0x7; 
-       u8 Rn = (opcode >> 3) & 0x7; 
-       u32 L = opcode & (1<<11);
-       u32 B = opcode & (1<<12);
+       uint32_t offset = (opcode >> 6) & 0x1f;
+       uint8_t Rd = (opcode >> 0) & 0x7; 
+       uint8_t Rn = (opcode >> 3) & 0x7; 
+       uint32_t L = opcode & (1<<11);
+       uint32_t B = opcode & (1<<12);
        char *mnemonic;
        char suffix = ' ';
-       u32 shift = 2;
+       uint32_t shift = 2;
 
        if (L)
        {
@@ -1761,7 +1759,7 @@ int evaluate_load_store_imm_thumb(u16 opcode, u32 address, arm_instruction_t *in
                shift = 0;
        }
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s%c r%i, [r%i, #0x%x]", address, opcode, mnemonic, suffix, Rd, Rn, offset<<shift);
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset<<shift);
        
        instruction->info.load_store.Rd = Rd;
        instruction->info.load_store.Rn = Rn;
@@ -1772,11 +1770,11 @@ int evaluate_load_store_imm_thumb(u16 opcode, u32 address, arm_instruction_t *in
        return ERROR_OK;
 }
 
-int evaluate_load_store_stack_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_load_store_stack_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u32 offset = opcode  & 0xff;
-       u8 Rd = (opcode >> 8) & 0x7; 
-       u32 L = opcode & (1<<11);
+       uint32_t offset = opcode  & 0xff;
+       uint8_t Rd = (opcode >> 8) & 0x7; 
+       uint32_t L = opcode & (1<<11);
        char *mnemonic;
 
        if (L)
@@ -1790,7 +1788,7 @@ int evaluate_load_store_stack_thumb(u16 opcode, u32 address, arm_instruction_t *
                mnemonic = "STR";
        }
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, [SP, #0x%x]", address, opcode, mnemonic, Rd, offset*4);
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [SP, #0x%" PRIx32 "]", address, opcode, mnemonic, Rd, offset*4);
        
        instruction->info.load_store.Rd = Rd;
        instruction->info.load_store.Rn = 13 /*SP*/;
@@ -1801,12 +1799,12 @@ int evaluate_load_store_stack_thumb(u16 opcode, u32 address, arm_instruction_t *
        return ERROR_OK;
 }
 
-int evaluate_add_sp_pc_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_add_sp_pc_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u32 imm = opcode  & 0xff;
-       u8 Rd = (opcode >> 8) & 0x7; 
-       u8 Rn;
-       u32 SP = opcode & (1<<11);
+       uint32_t imm = opcode  & 0xff;
+       uint8_t Rd = (opcode >> 8) & 0x7; 
+       uint8_t Rn;
+       uint32_t SP = opcode & (1<<11);
        char *reg_name;
 
        instruction->type = ARM_ADD;
@@ -1822,7 +1820,7 @@ int evaluate_add_sp_pc_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
                Rn = 15;
        }
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tADD r%i, %s, #0x%x", address, opcode, Rd,reg_name, imm*4);
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tADD r%i, %s, #0x%" PRIx32 "", address, opcode, Rd,reg_name, imm*4);
 
        instruction->info.data_proc.variant = 0 /* immediate */;
        instruction->info.data_proc.Rd = Rd;
@@ -1832,10 +1830,10 @@ int evaluate_add_sp_pc_thumb(u16 opcode, u32 address, arm_instruction_t *instruc
        return ERROR_OK;
 }
 
-int evaluate_adjust_stack_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_adjust_stack_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u32 imm = opcode  & 0x7f;
-       u8 opc = opcode & (1<<7);
+       uint32_t imm = opcode  & 0x7f;
+       uint8_t opc = opcode & (1<<7);
        char *mnemonic;
 
        
@@ -1850,7 +1848,7 @@ int evaluate_adjust_stack_thumb(u16 opcode, u32 address, arm_instruction_t *inst
                mnemonic = "ADD";
        }
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s SP, #0x%x", address, opcode, mnemonic, imm*4);
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s SP, #0x%" PRIx32 "", address, opcode, mnemonic, imm*4);
 
        instruction->info.data_proc.variant = 0 /* immediate */;
        instruction->info.data_proc.Rd = 13 /*SP*/;
@@ -1860,24 +1858,24 @@ int evaluate_adjust_stack_thumb(u16 opcode, u32 address, arm_instruction_t *inst
        return ERROR_OK;
 }
 
-int evaluate_breakpoint_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_breakpoint_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u32 imm = opcode  & 0xff;
+       uint32_t imm = opcode  & 0xff;
        
        instruction->type = ARM_BKPT;
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tBKPT 0x%02x", address, opcode, imm);
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBKPT 0x%02" PRIx32 "", address, opcode, imm);
 
        return ERROR_OK;
 }
 
-int evaluate_load_store_multiple_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u32 reg_list = opcode  & 0xff;
-       u32 L = opcode & (1<<11);
-       u32 R = opcode & (1<<8);
-       u8 Rn = (opcode >> 8) & 7;
-       u8 addr_mode = 0 /* IA */;
+       uint32_t reg_list = opcode  & 0xff;
+       uint32_t L = opcode & (1<<11);
+       uint32_t R = opcode & (1<<8);
+       uint8_t Rn = (opcode >> 8) & 7;
+       uint8_t addr_mode = 0 /* IA */;
        char reg_names[40];
        char *reg_names_p;
        char *mnemonic;
@@ -1929,7 +1927,7 @@ int evaluate_load_store_multiple_thumb(u16 opcode, u32 address, arm_instruction_
        else /* invalid op : no registers */
                reg_names[0] = '\0';
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s %s{%s}", address, opcode, mnemonic, ptr_name,reg_names);
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s %s{%s}", address, opcode, mnemonic, ptr_name,reg_names);
 
        instruction->info.load_store_multiple.register_list = reg_list;
        instruction->info.load_store_multiple.Rn = Rn;
@@ -1938,22 +1936,22 @@ int evaluate_load_store_multiple_thumb(u16 opcode, u32 address, arm_instruction_
        return ERROR_OK;
 }
 
-int evaluate_cond_branch_thumb(u16 opcode, u32 address, arm_instruction_t *instruction)
+int evaluate_cond_branch_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
-       u32 offset = opcode  & 0xff;
-       u8 cond = (opcode >> 8) & 0xf;
-       u32 target_address;
+       uint32_t offset = opcode  & 0xff;
+       uint8_t cond = (opcode >> 8) & 0xf;
+       uint32_t target_address;
 
        if (cond == 0xf)
        {
                instruction->type = ARM_SWI;
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tSWI 0x%02x", address, opcode, offset);
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tSWI 0x%02" PRIx32 , address, opcode, offset);
                return ERROR_OK;
        }
        else if (cond == 0xe)
        {
                instruction->type = ARM_UNDEFINED_INSTRUCTION;
-               snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
+               snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
                return ERROR_OK;
        }
 
@@ -1963,7 +1961,7 @@ int evaluate_cond_branch_thumb(u16 opcode, u32 address, arm_instruction_t *instr
        
        target_address = address + 4 + (offset<<1);
 
-       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tB%s 0x%8.8x", address, opcode,
+       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tB%s 0x%8.8" PRIx32 , address, opcode,
                         arm_condition_strings[cond], target_address);
        
        instruction->type = ARM_B;
@@ -1973,7 +1971,7 @@ int evaluate_cond_branch_thumb(u16 opcode, u32 address, arm_instruction_t *instr
        return ERROR_OK;
 }
 
-int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instruction)
+int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
        /* clear fields, to avoid confusion */
        memset(instruction, 0, sizeof(arm_instruction_t));
@@ -2044,7 +2042,7 @@ int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instructio
                else
                {
                        instruction->type = ARM_UNDEFINED_INSTRUCTION;
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
                        return ERROR_OK;
                }
        }
@@ -2067,7 +2065,7 @@ int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instructio
                if ((opcode & 0xf801) == 0xe801)
                {
                        instruction->type = ARM_UNDEFINED_INSTRUCTION;
-                       snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+                       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
                        return ERROR_OK;
                }
                else
@@ -2076,7 +2074,7 @@ int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instructio
                }
        }
 
-       ERROR("should never reach this point (opcode=%04x)",opcode);
+       LOG_ERROR("should never reach this point (opcode=%04x)",opcode);
        return -1;
 }
 
@@ -2110,7 +2108,7 @@ int arm_access_size(arm_instruction_t *instruction)
        }
        else
        {
-               ERROR("BUG: instruction type %i isn't a load/store instruction", instruction->type);
+               LOG_ERROR("BUG: instruction type %i isn't a load/store instruction", instruction->type);
                return 0;
        }
 }