ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
};
-typedef struct arm_b_bl_bx_blx_instr_s
+struct arm_b_bl_bx_blx_instr
{
int reg_operand;
uint32_t target_address;
-} arm_b_bl_bx_blx_instr_t;
+};
union arm_shifter_operand
{
} register_shift;
};
-typedef struct arm_data_proc_instr_s
+struct arm_data_proc_instr
{
int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
uint8_t S;
uint8_t Rn;
uint8_t Rd;
union arm_shifter_operand shifter_operand;
-} arm_data_proc_instr_t;
+};
-typedef struct arm_load_store_instr_s
+struct arm_load_store_instr
{
uint8_t Rd;
uint8_t Rn;
uint8_t shift_imm;
} reg;
} offset;
-} arm_load_store_instr_t;
+};
typedef struct arm_load_store_multiple_instr_s
{
unsigned instruction_size;
union {
- arm_b_bl_bx_blx_instr_t b_bl_bx_blx;
- arm_data_proc_instr_t data_proc;
- arm_load_store_instr_t load_store;
+ struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
+ struct arm_data_proc_instr data_proc;
+ struct arm_load_store_instr load_store;
arm_load_store_multiple_instr_t load_store_multiple;
} info;
} arm_instruction_t;
-extern int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction);
-extern int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction);
-extern int thumb2_opcode(target_t *target, uint32_t address,
+int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
+ arm_instruction_t *instruction);
+int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
+ arm_instruction_t *instruction);
+int thumb2_opcode(target_t *target, uint32_t address,
arm_instruction_t *instruction);
-extern int arm_access_size(arm_instruction_t *instruction);
+int arm_access_size(arm_instruction_t *instruction);
#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])