Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / arm_dpm.c
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 6bfe355ba2e0ed50ea40c687b77dba32f802c8fe..9f3a444afc5dae407e5c8a03783ef666b02e7107 100644 (file)
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -1,18 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
 /*
  * Copyright (C) 2009 by David Brownell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #ifdef HAVE_CONFIG_H
@@ -50,7 +39,7 @@
 
 /* Read coprocessor */
 static int dpm_mrc(struct target *target, int cpnum,
-       uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
+       uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
        uint32_t *value)
 {
        struct arm *arm = target_to_arm(target);
@@ -62,12 +51,35 @@ static int dpm_mrc(struct target *target, int cpnum,
                return retval;
 
        LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
-               (int) op1, (int) CRn,
-               (int) CRm, (int) op2);
+               (int) op1, (int) crn,
+               (int) crm, (int) op2);
 
        /* read coprocessor register into R0; return via DCC */
        retval = dpm->instr_read_data_r0(dpm,
-                       ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
+                       ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
+                       value);
+
+       /* (void) */ dpm->finish(dpm);
+       return retval;
+}
+
+static int dpm_mrrc(struct target *target, int cpnum,
+       uint32_t op, uint32_t crm, uint64_t *value)
+{
+       struct arm *arm = target_to_arm(target);
+       struct arm_dpm *dpm = arm->dpm;
+       int retval;
+
+       retval = dpm->prepare(dpm);
+       if (retval != ERROR_OK)
+               return retval;
+
+       LOG_DEBUG("MRRC p%d, %d, r0, r1, c%d", cpnum,
+                (int)op, (int)crm);
+
+       /* read coprocessor register into R0, R1; return via DCC */
+       retval = dpm->instr_read_data_r0_r1(dpm,
+                       ARMV5_T_MRRC(cpnum, op, 0, 1, crm),
                        value);
 
        /* (void) */ dpm->finish(dpm);
@@ -75,7 +87,7 @@ static int dpm_mrc(struct target *target, int cpnum,
 }
 
 static int dpm_mcr(struct target *target, int cpnum,
-       uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
+       uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
        uint32_t value)
 {
        struct arm *arm = target_to_arm(target);
@@ -87,18 +99,41 @@ static int dpm_mcr(struct target *target, int cpnum,
                return retval;
 
        LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
-               (int) op1, (int) CRn,
-               (int) CRm, (int) op2);
+               (int) op1, (int) crn,
+               (int) crm, (int) op2);
 
        /* read DCC into r0; then write coprocessor register from R0 */
        retval = dpm->instr_write_data_r0(dpm,
-                       ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
+                       ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
                        value);
 
        /* (void) */ dpm->finish(dpm);
        return retval;
 }
 
+static int dpm_mcrr(struct target *target, int cpnum,
+       uint32_t op, uint32_t crm, uint64_t value)
+{
+       struct arm *arm = target_to_arm(target);
+       struct arm_dpm *dpm = arm->dpm;
+       int retval;
+
+       retval = dpm->prepare(dpm);
+       if (retval != ERROR_OK)
+               return retval;
+
+       LOG_DEBUG("MCRR p%d, %d, r0, r1, c%d", cpnum,
+               (int)op, (int)crm);
+
+       /* read DCC into r0, r1; then write coprocessor register from R0, R1 */
+       retval = dpm->instr_write_data_r0_r1(dpm,
+                       ARMV5_T_MCRR(cpnum, op, 0, 1, crm), value);
+
+       /* (void) */ dpm->finish(dpm);
+
+       return retval;
+}
+
 /*----------------------------------------------------------------------*/
 
 /*
@@ -398,7 +433,7 @@ fail:
  * or running debugger code.
  */
 static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
-       struct dpm_bpwp *xp, int *set_p)
+       struct dpm_bpwp *xp, bool *set_p)
 {
        int retval = ERROR_OK;
        bool disable;
@@ -473,7 +508,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
                        struct breakpoint *bp = dbp->bp;
 
                        retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
-                                       bp ? &bp->set : NULL);
+                                       bp ? &bp->is_set : NULL);
                        if (retval != ERROR_OK)
                                goto done;
                }
@@ -485,7 +520,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
                struct watchpoint *wp = dwp->wp;
 
                retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
-                               wp ? &wp->set : NULL);
+                               wp ? &wp->is_set : NULL);
                if (retval != ERROR_OK)
                        goto done;
        }
@@ -514,7 +549,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
                                continue;
                        if (arm->cpsr == cache->reg_list + i)
                                continue;
-                       if (!cache->reg_list[i].dirty)
+                       if (!cache->reg_list[i].exist || !cache->reg_list[i].dirty)
                                continue;
 
                        r = cache->reg_list[i].arch_info;
@@ -763,7 +798,7 @@ static int arm_dpm_full_context(struct target *target)
                for (unsigned i = 0; i < cache->num_regs; i++) {
                        struct arm_reg *r;
 
-                       if (cache->reg_list[i].valid)
+                       if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
                                continue;
                        r = cache->reg_list[i].arch_info;
 
@@ -929,7 +964,7 @@ static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
        uint32_t control;
 
        /* this hardware doesn't support data value matching or masking */
-       if (wp->value || wp->mask != ~(uint32_t)0) {
+       if (wp->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) {
                LOG_DEBUG("watchpoint values and masking not supported");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }
@@ -1010,7 +1045,7 @@ void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
                        /* ?? */
                        break;
        }
-       dpm->wp_pc = addr;
+       dpm->wp_addr = addr;
 }
 
 /*----------------------------------------------------------------------*/
@@ -1061,7 +1096,7 @@ int arm_dpm_setup(struct arm_dpm *dpm)
 {
        struct arm *arm = dpm->arm;
        struct target *target = arm->target;
-       struct reg_cache *cache = 0;
+       struct reg_cache *cache = NULL;
 
        arm->dpm = dpm;
 
@@ -1070,7 +1105,7 @@ int arm_dpm_setup(struct arm_dpm *dpm)
        arm->read_core_reg = arm_dpm_read_core_reg;
        arm->write_core_reg = arm_dpm_write_core_reg;
 
-       if (arm->core_cache == NULL) {
+       if (!arm->core_cache) {
                cache = arm_build_reg_cache(target, arm);
                if (!cache)
                        return ERROR_FAIL;
@@ -1081,6 +1116,8 @@ int arm_dpm_setup(struct arm_dpm *dpm)
        /* coprocessor access setup */
        arm->mrc = dpm_mrc;
        arm->mcr = dpm_mcr;
+       arm->mrrc = dpm_mrrc;
+       arm->mcrr = dpm_mcrr;
 
        /* breakpoint setup -- optional until it works everywhere */
        if (!target->type->add_breakpoint) {
@@ -1088,9 +1125,11 @@ int arm_dpm_setup(struct arm_dpm *dpm)
                target->type->remove_breakpoint = dpm_remove_breakpoint;
        }
 
-       /* watchpoint setup */
-       target->type->add_watchpoint = dpm_add_watchpoint;
-       target->type->remove_watchpoint = dpm_remove_watchpoint;
+       /* watchpoint setup -- optional until it works everywhere */
+       if (!target->type->add_watchpoint) {
+               target->type->add_watchpoint = dpm_add_watchpoint;
+               target->type->remove_watchpoint = dpm_remove_watchpoint;
+       }
 
        /* FIXME add vector catch support */
 
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)